MT9315 Zarlink Semiconductor, MT9315 Datasheet
MT9315
Related parts for MT9315
MT9315 Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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... -24 -> +21dB - User ADV + AGC Gain NLP FORMAT ENA1 ENA2 Figure 1 - Functional Block Diagram MT9315 CMOS Acoustic Echo Canceller Advance Information ISSUE 3 February 1999 Ordering Information 28 Pin PLCC 28 Pin PDIP - Linear/ /A-Law Micro Interface Howling Controller Filter ...
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... MT9315 1 ENA1 2 MD1 ENA2 3 4 MD2 5 Rin PDIP Sin 6 7 VSS 8 MCLK LAW 13 FORMAT 14 PWRDN Pin Description Pin # Name 1 ENA1 SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS is selected. ...
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... FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both serial pcm ports. 14 PWRDN Power-down (Input). An active low resets the device and puts the MT9315 into a low-power stand-by mode. 15 Connect (Output) ...
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... Patent Pending) After echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible. The MT9315 uses an NLP to remove low level residual echo signals which are not comprised of background noise. The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which disables the NLP during double-talk periods ...
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... This gain is adjustable from -24dB to +21dB in 3dB steps important to use ONLY this user gain function to adjust the speaker volume. The user gain function in the MT9315 is optimally placed between the two echo cancellers such that no reconvergence is necessary after gain changes. ...
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... MT9315 Power Down Forcing the PWRDN pin to logic low, will put the MT9315 into a power down state. In this state all internal clocks are halted, the DATA1, Sout and Rout pins are tristated. The user should hold the PWRDN 200 msec on Power-up. This will insure that the device powers proper state ...
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... DATA2 becomes the data receive pin. The MT9315 supports Motorola half-duplex processor mode (CPOL=0 and CPHA=0). This means that during a write to the MT9315, by the Motorola processor, output data from the DATA1 pin must be ignored. This also means that input data on the DATA2 pin is ignored by the MT9315 during a valid read by the Motorola processor ...
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... MT9315 C4i F0i PORT1 Rin Sout PORT2 Sin Rout outputs = High impedance inputs = don’t care In ST-BUS Mode 1, echo canceller I/O channels are assigned to ST-BUS timeslot 0. Note that the user could configure PORT1 and PORT2 into different ST-BUS modes ...
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... ECA MT9315 ...
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... SCLK CS This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT9315. The MT9315: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high ...
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... High Impedance Transmit SCLK CS This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT9315. The MT9315: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high ...
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... MT9315 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Input Voltage 3 Output Voltage Swing 4 Continuous Current on any digital pin 5 Storage Temperature 6 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Supply Voltage ...
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... SSS t 15 SSH t 10 DIS t 15 DIH t 20 F0iS t 20 F0iH t 80 DSD t 80 ASHZ t 20 DSH t 20 DSS MT9315 ) unless otherwise stated. Units Conditions/Notes unless SS Max Units Test Notes ns ns 20.5 MHz ns ns 7900 =150pF =150pF L ...
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... MT9315 AC Electrical Characteristics Characteristics 1 Input Data Setup 2 Input Data Hold 3 Output Data Delay 4 Serial Clock Period 5 SCLK Pulse Width High 6 SCLK Pulse Width Low 7 CS Setup-Intel 8 CS Setup-Motorola 9 CS Hold Output High Impedance † Timing is over recommended temperature range and recommended power supply voltages. ...
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... BCH t BCP t t DIS DIH Bit 1 Figure 11 - SSI Data Port Timing Bit 0 Bit DSD C4H t C4L t t DSS DSH Bit 0 Bit 1 Figure 12 - ST-BUS Data Port Timing MT9315 AHZ BCL SSH ASHZ ...
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... MT9315 (1, 2) DATA1 V H (2) SCLK CSSI Notes: 1. CMOS output 2. TTL input compatible 3. CMOS input (see Table 8 for symbol definitions (2) DATA2 (Input IDS IDH V H (2) SCLK CSSM (1) DATA1 (Output) Figure 14 - Motorola Serial Microport Timing Notes: 1 ...
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... This bit is also ignored if bit register is set to zero Main Control Register (MC MUTE_S BYPASS NB NLP- INJ- HPF- Line Echo Canceller Control Register (LEC NLP- INJ- HPF- MT9315 AGC- AH- RESET LSB HCLR ECBY ADAPT- LSB HCLR ECBY ADAPT- ...
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... MT9315 Address: Acoustic Echo Canceller Status Register 22h Read 7 6 Power Up - ACMUND Reset 00h MSB NBS When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not been detected in the Sin/Sout path NB LOGICAL OR of the status bit NBS + NBR from LSR Register ...
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... RIPD RIPD RIPD Receive (Rin) Peak Detect Register RIPD RIPD RIPD REPD REPD REPD MT9315 1 (RIPD1 RIPD RIPD RIPD (RIPD2 RIPD RIPD RIPD (REPD1 REPD REPD REPD ...
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... MT9315 Address: Receive (Rin) ERROR Peak Detect Register 19h Read 7 6 Power Up REPD REPD 15 Reset 00h MSB REPD8 REPD9 See above description REPD10 REPD11 REPD12 REPD13 REPD14 REPD15 Address: Receive (Rout) Peak Detect Register 3Ah Read 7 6 Power Up ROPD ROPD 7 Reset 00h ...
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... SIPD SIPD SIPD Send (Sin) Peak Detect Register SIPD SIPD SIPD SEPD SEPD SEPD MT9315 1 (SIPD1 SIPD SIPD SIPD (SIPD2 SIPD SIPD SIPD (SEPD1 SEPD SEPD SEPD ...
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... MT9315 Address: Send ERROR Peak Detect Register 39h Read 7 6 Power Up SEPD SEPD 15 Reset 00h MSB SEPD8 SEPD9 SEPD10 SEPD11 See Above description SEPD12 SEPD13 SEPD14 SEPD15 Address: 1Ah Read 7 6 Power Up SOPD SOPD 7 Reset 00h MSB SOPD 0 SOPD 1 These peak detector registers allow the user to monitor the Send out signal (Sout) peak level at reference point S3 (see Figure #1). The information is in 16-bit 2’ ...
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... L_AS A_AS A_AS A_AS A_AS A_AS A_AS L_AS L_AS L_AS MT9315 1 (A_AS1 A_AS A_AS A_AS LSB 2 (A_AS2 A_AS A_AS A_AS LSB 1 (L_AS1 L_AS L_AS L_AS ...
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... MT9315 Address: Line Echo Canceller Adaptation Speed Register 1Dh R Power Up L_AS L_AS 15 Reset 08h MSB L_AS 8 L_AS 9 L_AS 10 See Above description L_AS 11 L_AS 12 L_AS 13 L_AS 14 L_AS 15 Address: 24h R Power Reset 80h MSB - - - RESERVED - - - - L This bit is used in conjunction with Rout Limiter Register 2. (See description below.) ...
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... Address: 03h Read 7 6 Power Up DRC DRC 2 Reset 40h MSB - - RESERVED - - DRC 0 DRC 1 Revision code of the device (=02). DRC 2 Sout Limiter Register Device Revision Code Register DRC - 0 1 MT9315 (SL (DRC LSB LSB 25 ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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