MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 7

• Manufacturer Part Number: MT9315
• Description: Acoustic Echo CANceller
• Manufacturer: Zarlink Semiconductor

MT9315
Power Down
Forcing the PWRDN pin to logic low, will put the
MT9315 into a power down state. In this state all
internal clocks are halted, the DATA1, Sout and Rout
pins are tristated.
The user should hold the PWRDN
200 msec on Power-up. This will insure that the
device powers up in a proper state.
The device will automatically begin the execution of
initialization routines when the PWRDN pin is
returned to logic high and a clock is applied to the
MCLK pin. The initialization routines execute for one
frame and will set the MT9315 to default register
values.
After power down, the user waits for 2 complete 8
KHz frames prior to writing to the device registers.
PCM Data I/O
The PCM data transfer for the MT9315 is provided
through two PCM ports. One port consists of Rin and
Sout pins while the second port consists of Sin and
Rout pins. The data are transferred through these
ports according to either ST-BUS or SSI conventions.
The device determines the convention by monitoring
the signal applied to the F0i pin. When a valid ST-
BUS frame pulse is applied to the F0i pin, the
MT9315 will assume ST-BUS operation. If F0i is tied
continuously to Vss, the MT9315 will assume SSI
operation.
ST-BUS Operation
The ST-BUS PCM interface conforms to Mitel’s ST-
BUS standard and it is used to transport 8 bit
companded PCM data (using one timeslot) or 16 bit
2’s complement linear PCM data (using two
timeslots). The MD1/ENA1 pins select the timeslot
on the Rin/Sout port while the MD2/ENA2 pin selects
the timeslot on the Sin/Rout port. See Table 2 and
Figures 3 to 6.
6
pin low for
SSI Operation
The SSI PCM interface consists of data input pins
(Rin, Sin), data output pins (Sout, Rout), a variable
rate bit clock (BCLK), and two enable pins (ENA1,
ENA2) to provide strobes for data transfers. The
active high enable may be either 8 or 16 BCLK
cycles in duration. Automatic detection of the data
type (8 bit companded or 16 bit 2’s complement
linear) is accomplished internally. The data type
cannot change dynamically from one frame to the
next.
In SSI operation, the frame boundary is determined
by the rising edge of the ENA1 enable strobe (see
Figure 7). The other enable strobe (ENA2) is used
for parsing input/output data and it must pulse within
125 microseconds of the rising edge of ENA1.
In SSI operation, the enable strobes may be a mixed
combination of 8 or 16 BCLK cycles allowing the
flexibility to mix 2’s complement linear data on one
port (e.g., Rin/Sout) with companded data on the
other port (e.g., Sin/Rout).
PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the
MT9315 is controlled through the LAW and FORMAT
pins. ITU-T G.711 companding curves for -Law and
A-Law are selected by the LAW pin. PCM coding
ITU-T G.711 and Sign-Magnitude are selected by the
FORMAT pin. See Table 4.
MD1
Enable Pins
Rin/Sout
0
0
1
1
PORT1
Enable Strobe Pin
ENA1
0
1
0
1
ENA1
ENA2
Table 3 - SSI Enable Strobe Pins
Table 2 - ST-BUS Mode Select
Mode 1. 8 bit companded PCM I/O on
timeslot 0
Mode 2. 8 bit companded PCM I/O on
timeslot 2.
Mode 3. 8 bit companded PCM I/O on
timeslot 2. Includes D & C channel
bypass in timeslots 0 & 1.
Mode 4. 16 bit 2’s complement linear
PCM I/O on timeslots 0 & 1.
ST-BUS Mode
Selection
Acoustic Side Echo Path (PORT 2)
Advance Information
Line Side Echo Path (PORT 1)
Designated PCM I/O Port
MD2
Enable Pins
Sin/Rout
0
0
1
1
PORT2
ENA2
0
1
0
1