MT93L00A Zarlink Semiconductor, MT93L00A Datasheet
MT93L00A
Related parts for MT93L00A
MT93L00A Summary of contents
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... Group 12 Group 13 Group 14 ECA/ECB ECA/ECB ECA/ECB Microprocessor Interface DS CS R/W A10-A0 DTA D7-D0 IRQ Figure 1 - Functional Block Diagram MT93L00A Preliminary Information ISSUE 2 Ordering Information MT93L00AB 100-Pin LQFP MT93L00AV 208-Ball LBGA - +85 C conforming to ITU-T or any combination of DD2 (1.8V) ODE Rout Group 3 Parallel to ECA/ECB Serial ...
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... VSS TRSTB IC0 RESETB IRQB DS CS R/W DTA VDD2 VSS DD1 MT93L00AB (100 pin LQFP) = 3.3V V DD2 Figure 2A - 100 Pin LQFP Preliminary Information IC0 IC0 IC0 VSS IC0 IC0 IC0 IC0 VDD2 C4ib Foib Rin Sin Rout ...
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... V V DD1 SS DD1 SS DD1 DD1 SS DD1 SS DD1 DTA IRQ DD1 DD1 DD1 Figure 2B - 208 Ball LBGA MT93L00A ICO Sin ODE ...
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... MT93L00A Pin Description PIN # 100 PIN 208-Ball LBGA LQFP A1,A3,A7,A11,A13,A15, 5, 18, 32, A16,B2,B4,B6,B8,B12, 42, 56, 69, B14,B15,B16,C3,C5,C7, 81, 98 C9,C11,C12,C13,C14, C16, D4,D8,D10,D12,D13,E3, E4,E14,F13,G3,G4,G7,G8, G9,G10,H7,H8,H9, H10,H13,H14,J7,J8,J9, J10,K7,K8,K9,K10,K13, K14,L3,L4,M13,M14,M15, N3,N4,N5,N7,N9,N11,N13, P2,P3,P5,P7,P9.P11,P13, P14,R2,R14,R15,R16,T1, T3,T7,T10, T14,T16 A5,A9,B10,C4,C8,C10,D3, 27, 48, 77, D5,D7,D9,D11,D14,E13, 100 F3,F4,F14,H3,H4,J13,J14, L13,L14,M3,M4,N6,N8, N10,N14,N15,P4,P6,P8, ...
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... PLL Ground. Must be connected to V PLLVss2 PLLV PLL Power Supply. Must be connected TMS Test Mode Select (3.3V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. MT93L00A Description SS DD2 5 ...
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... MT93L00A Pin Description (continued) PIN # 100 PIN 208-Ball LBGA LQFP Device Overview The MT93L00 architecture contains cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, ...
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... DTDT Example: For DTDT = 0.5625 (-5dB), the Path Change Detector Integrated into the MT93L00A is a Path Change Detector. This permits fast reconvergence when a major change occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is achieved, but at a much slower speed ...
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... MT93L00A optional path clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection of a major path change. Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible ...
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... Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo cancellation is required. Back-to-Back configuration is selected by writing “1” into the BBM bit of both Control Register A1 and Control Register given group of echo MT93L00A 32 echo the two echo ...
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... MT93L00A cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured into Back-to-Back. Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a transmission device or between two codecs for echo control on analog trunks. Extended Delay configuration In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller ...
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... Figure 9). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 10). 125 sec Channel 1 Channel 30 MT93L00A Channel 31 11 ...
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... MT93L00A Base Base Echo Canceller A Addr + Addr + 00h Control Reg A1 20h Control Reg B1 Control Reg 2 Control Reg 2 01h 21h Status Reg Status Reg 02h 22h Reserved Reserved 03h 23h Flat Delay Reg Flat Delay Reg 04h 24h Reserved Reserved 05h 25h ...
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... FIFO memory. The IRQ always returns high after a read access to the , for the specific H Interrupt FIFO Register. The IRQ pin will toggle low for each pending interrupt. MT93L00A is in Power Down mode Nb_of_groups + 3. ...
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... MT93L00A After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 7 for address mapping of Status register). The TD bit indicates the presence of a Tone Disable ...
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... Note: Do not enable both Extended-Delay and BBM configurations at the same time. Control Register B1 bit reserved bit and should be written “0”. Read/Write Address Reset Value: AdpDis 0 ExtDl Read/Write Address AdpDis 1 0 Reset Value: Description MT93L00A + Base Address Base Address ...
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... MT93L00A Echo Canceller A, Control Register A2 Echo Canceller B, Control Register TDis PHDis NLPDis AutoTD NBDis Bit Name 7 TDis When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put into power down mode ...
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... Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100Hz tone Logic high indicates the presence of a narrow-band signal on Rin. Read Address: Read Address res TDG NB Reset Value: Description MT93L00A 02 + Base Address Base Address ...
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... MT93L00A Echo Canceller A, Flat Delay Register (FD) Echo Canceller B, Flat Delay Register (FD Echo Canceller A, Decay Step Number Register (NS) Echo Canceller B, Decay Step Number Register (NS Echo Canceller A, Decay Step Size Control Register (SSC) ...
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... Read/Write Address: 0Ah + Base Address Read/Write Address: 2Ah + Base Address • 80h = 72h). Similarly, to scale dB, use a value of (dec) • 80h = 8Fh). (dec) MT93L00A + Base Address H + Base Address Base Address H + Base Address Power Reset Value 74h 19 ...
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... MT93L00A Echo Canceller A, Injection Rate (IR) Echo Canceller B, Injection Rate (IR The NLP ramps-in comfort noise during the initial background noise estimation stage. This register provides control over the ramp-in speed. Higher values will increase the ramp-in speed. ...
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... Read Address: 10h + Base Address Read Address: 30h + Base Address MT93L00A Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A 21 ...
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... MT93L00A Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: 15h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address: 35h + Base Address DTDT DTDT DTDT DTDT Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address: 14h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 1 Read/Write Address: 34h + Base Address ...
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... Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. Read/Write Address: 400 Format LAW PWUP Reset Value: Description . . MT93L00A ...
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... MT93L00A Main Control Register 1 Main Control Register 2 Main Control Register 3 Main Control Register 4 Main Control Register 5 Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register 10 Main Control Register 11 Main Control Register 12 Main Control Register 13 Main Control Register 14 ...
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... Interrupt FIFO Register. When low, normal operation is selected. Read Address Reset Value: Description Read/Write Address: 411 res res Tirq Reset Value: Description MT93L00A 410 (Read only ...
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... MT93L00A Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage (V ) DD1 2 Core Supply Voltage (V DD2 3 Input Voltage 4 Input Voltage on any 5V Tolerant I/O pins 5 Continuous Current at digital outputs 6 Package power dissipation 7 Storage temperature * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ...
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... Serial Streams for ST-BUS and GCI Backplanes ‡ Sym Min Typ Max t 10 SIS t 10 SIH t 60 SOD t 30 ODE , with timing corrected to cancel time taken to discharge C L MT93L00A Units Conditions Units Notes Units Test Conditions ...
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... MT93L00A F0i t C4i Rout/Sout Bit 0, Channel 31 Rin/Sin Bit 0, Channel 31 Figure 9 - ST-BUS Timing at 2.048 Mb/s F0i t FPS C4i Sout/Rout Bit 7, Channel 31) Sin/Rin Bit 7, Channel 31) Figure 10 - GCI Interface Timing at 2.048 Mb/s Sout/Rout 28 t FPW FPS FPH t SOD Bit 7, Channel 0 Bit 6, Channel SIS ...
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... DD1 MCLK † - Master Clock - Voltages are with respect to ground (V ‡ Sym Min Typ Max f 19.0 20.0 21.0 MCF0 f 9.5 10.0 10.5 MCF1 t 20 MCL t 20 MCH t MCH t MCL Figure 12 - Master Clock MT93L00A ). unless otherwise stated. SS Units Notes MHz MHz ...
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... MT93L00A AC Electrical Characteristics Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS rising 7 Data delay on read 8 Data hold on read 9 Data setup on write 10 Data hold on write 11 Acknowledgment delay 12 Acknowledgment hold time 13 IRQ delay † ...
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... Preliminary Information Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard MS-026 MT93L00AB 100-Pin LQFP - B Suffix 100-Pin Dim Min Max A - 0.063 (1.60) A1 0.002 0.006 (0.05) (0.15) A2 0.053 0.057 (1.35) (1.45) b 0.007 0.011 (0.17) (0.27) D 0.630 (16.00 BSC) D1 0.551 (14.00 BSC) e 0.020 (0.50 BSC) E 0.630 (16.00 BSC) E1 0.551 (14.00 BSC) ...
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... 1.215 REF 15.00 0.20 R0.25 Typ. 0.54 0.05 Seating Plane C (0.36) 32 0.50 (3X) REF. Ø *The ball diamter and stand-off different 1.30 0.20 0.30 ~ 0.5 MT93L00AV 208-Ball LBGA Preliminary Information 0.40 ~ 0.60 (208X ...
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