MT93L00A Zarlink Semiconductor, MT93L00A Datasheet - Page 8

• Manufacturer Part Number: MT93L00A
• Manufacturer: Zarlink Semiconductor

MT93L00A
optional path clearing feature can be enabled by
setting the PathClr bit in Control Register A3/B3 to
"1". With path clearing turned on, the existing echo
channel estimate will also be cleared (i.e. the
adaptive filter will be filled with zeroes) upon
detection of a major path change.
Non-Linear Processor (NLP)
After echo cancellation, there is always a small
amount of residual echo which may still be audible.
The MT93L00 uses an NLP to remove residual echo
signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This
threshold depends upon the level of the Rin (Lrin)
reference signal as well as the programmed value of
the
(NLPTHR). TSUP can be calculated by the following
equation:
When the level of residual error signal falls below
TSUP, the NLP is activated further attenuating the
residual signal by an additional 36 dB. To prevent a
perceived decrease in background noise due to the
activation of the NLP, a spectrally-shaped comfort
noise, equivalent in power level to the background
noise, is injected. This keeps the perceived noise
level constant. Consequently, the user does not hear
the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the
NLPDis bit to “1” in Control Register 2.
The NLPTHR register is 16 bits wide. The register
value in hexadecimal can be calculated with the
following equation:
The comfort noise injector can be disabled by setting
the INJDis bit to “1” in Control Register A1/B1. It
should be noted that the NLPTHR is valid and the
comfort noise injection is active only when the NLP is
enabled.
If the comfort noise injector is unable to correctly
match the level of the background noise (because of
peculiar spectral characteristics, for example), the
8
where NLPTHR is the Non-Linear Processor
Threshold register value and Lrin is the relative
power level expressed in dBm0.
Non-Linear
NLPTHR
TSUP = Lrin + 20log
where 0 < NLPTHR
(hex)
Processor
= hex(NLPTHR
10
(NLPTHR)
Threshold
(dec)
(dec)
< 1
* 32768)
register
injected level can be fine-tuned using the Noise
Scaling register. A neutral value of 80
prevent any scaling. Values less than 80
reduce the noise level, values greater than 80
will increase the noise level. The scaling is done
linearly.
Example: To decrease the comfort noise level
The default factory setting for the Noise Scaling
register should be adequate for most operating
environments. It is unlikely that it will need to be
changed. It has also been set to a value which will
ensure G.168 compliance.
Disable Tone Detector
G.165 recommendation defines the disable tone as
having the following characteristics: 2100 Hz
( 21Hz) sine wave, a power level between -6 to
-31dBm0, and a phase reversal of 180 degrees ( 25
degrees) every 450ms ( 25ms). If the disable tone
is present for a minimum of one second with at least
one phase reversal, the Tone Detector will trigger.
G.164 recommendation defines the disable tone as a
2100 Hz ( 21Hz) sine wave with a power level
between 0 to -31dBm0. If the disable tone is present
for a minimum of 400 milliseconds, with or without
phase reversal, the Tone Detector will trigger.
The MT93L00 has two Tone Detectors per channels
(for a total of 64) in order to monitor the occurrence
of a valid disable tone on both Rin and Sin. Upon
detection of a disable tone, TD bit of the Status
Register will indicate logic high and an interrupt is
generated (i.e. IRQ pin low). Refer to Figure 4 and to
the Interrupts section.
Rin
Sin
Rin
Sin
Figure 4 - Disable Tone Detection
by 3 dB, the register value would be
10 ^ (-3 / 20) • 128
= 0.71 • 128
= 91
= 5B
Tone
Tone
Tone
Tone
(dec)
(hex)
Echo Canceller A
Echo Canceller B
Detector
Detector
Detector
Detector
Preliminary Information
Status reg
Status reg
TD
TD bit
ECA
ECB
(hex)
(hex)
bit
(hex)
will
will