MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet
MT93L00AB
Related parts for MT93L00AB
MT93L00AB Summary of contents
Page 1
... ECA/ECB ECA/ECB Group 12 Group 13 Group 14 ECA/ECB ECA/ECB ECA/ECB Microprocessor Interface DS CS R/W A10-A0 DTA D7-D0 IRQ Figure 1 - Functional Block Diagram MT93L00A Preliminary Information ISSUE 3 Ordering Information MT93L00AB 100-Pin LQFP MT93L00AV 208-Ball LBGA - +85 C conforming to ITU-T or any combination of DD2 (1.8V) ODE Rout Group 3 Parallel ...
Page 2
... VSS TRSTB IC0 RESETB IRQB DS CS R/W DTA VDD2 VSS DD1 MT93L00AB (100 pin LQFP) = 3.3V V DD2 Figure 2A - 100 Pin LQFP Preliminary Information IC0 IC0 IC0 VSS IC0 IC0 IC0 IC0 VDD2 C4ib Foib Rin Sin Rout ...
Page 3
Preliminary Information c4i V ICO DD1 F0i B ICO V ICO V SS DD1 C ICO ICO DD1 NC ICO DD1 ...
Page 4
MT93L00A Pin Description PIN # 100 PIN 208-Ball LBGA LQFP A1,A3,A7,A11,A13,A15, 5, 18, 32, A16,B2,B6,B8,B12, 42, 56, 69, B14,B15,B16,C3,C5,C7, 81, 98 C9,C11,C12,C13,C14, C16, D4,D8,D10,D12,D13,E3, E4,E14,F13,G3,G4,G7,G8, G9,G10,H7,H8,H9, H10,H13,H14,J7,J8,J9, J10,K7,K8,K9,K10,K13, K14,L3,L4,M13,M14,M15, N3,N4,N5,N7,N9,N11,N13, P2,P3,P5,P7,P9.P11,P13, P14,R2,R14,R15,R16,T1, T3,T7,T10, T14,T16 A5,A9,B4,B10,C4,C8,C10, 27, 48, 77, D3,D5,D7,D9,D11,D14,E1 100 ...
Page 5
Preliminary Information Pin Description (continued) PIN # 100 PIN 208-Ball LBGA LQFP T2,T4,T6,T8,T9,T11, 15,16,17, T13,T15 19,20,21, 22,23 P16,N16,M16,L16,K16, 28,29,30,31, J16,H16,G16,F16,E16, 33,34,35,36, D16 38,39,40 B13 B11 ...
Page 6
MT93L00A Pin Description (continued) PIN # 100 PIN 208-Ball LBGA LQFP Device Overview The MT93L00 architecture contains cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller ...
Page 7
Preliminary Information /A-Law/ Sin Linear (channel N) Disable Tone Detector Programmable ST-BUS Bypass PORT2 Instability Detector Linear/ Rout (channel N) Figure 3 - Echo Canceller Functional Block Diagram echo estimation. In Normal configuration, the first section is dedicated to channel ...
Page 8
MT93L00A optional path clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled ...
Page 9
Preliminary Information Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. ...
Page 10
MT93L00A cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured into Back-to-Back. Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a transmission device or between two codecs for ...
Page 11
Preliminary Information at least one frame (125 s) in order to properly clear the filter. Disable Adaptation When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The adaptation process is halted, however, ...
Page 12
MT93L00A Base Base Echo Canceller A Addr + Addr + 00h Control Reg A1 20h Control Reg B1 Control Reg 2 Control Reg 2 01h 21h Status Reg Status Reg 02h 22h Reserved Reserved 03h 23h Flat Delay Reg Flat ...
Page 13
Preliminary Information Channel Ctrl/Stat Registers Group 0 Echo Cancellers Channel Ctrl/Stat Registers Registers Channel Ctrl/Stat Registers Group 1 Echo Cancellers Channel Ctrl/Stat Registers Registers Groups 2 --> 14 ...
Page 14
MT93L00A After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 7 for address mapping of ...
Page 15
Preliminary Information Register Descriptions Echo Canceller A, Control Register Reset INJDis BBM PAD Bypass Echo Canceller B, Control Register Reset INJDis BBM PAD Bypass Bit Name 7 Reset ...
Page 16
MT93L00A Echo Canceller A, Control Register A2 Echo Canceller B, Control Register TDis PHDis NLPDis AutoTD NBDis Bit Name 7 TDis When high, tone detection is disabled. When low, tone detection is enabled. When ...
Page 17
Preliminary Information Echo Canceller A, Status Register Echo Canceller B, Status Register res TD DTDet res res Bit Name 1 TDG Tone detection status bit gated with the AutoTD bit. Logic high indicates that AutoTD ...
Page 18
MT93L00A Echo Canceller A, Flat Delay Register (FD) Echo Canceller B, Flat Delay Register (FD Echo Canceller A, Decay Step Number Register (NS) Echo Canceller B, Decay Step Number ...
Page 19
Preliminary Information Echo Canceller A, Control Register A3 Echo Canceller B, Control Register res res res res RingClr Bit Name 7-4 res Reserved bits. Must always be set to zero for normal operation. 3 ...
Page 20
MT93L00A Echo Canceller A, Injection Rate (IR) Echo Canceller B, Injection Rate (IR The NLP ramps-in comfort noise during the initial background noise estimation stage. This register provides ...
Page 21
Preliminary Information Echo Canceller A, Rin Peak Detect Register 2 (RP) Echo Canceller B, Rin Peak Detect Register 2 (RP Echo Canceller A, Rin Peak Detect Register 1 ...
Page 22
MT93L00A Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: 15h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address: 35h + Base Address DTDT DTDT DTDT DTDT Echo ...
Page 23
Preliminary Information Main Control Register 0 (EC group WR_all ODE MIRQ MTDBI MTDAI Bit Name 7 WR_all Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000h to 0003Fh ...
Page 24
MT93L00A Main Control Register 1 Main Control Register 2 Main Control Register 3 Main Control Register 4 Main Control Register 5 Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register ...
Page 25
Preliminary Information Interrupt FIFO Register IRQ Bit Name 7 IRQ Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates ...
Page 26
MT93L00A Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage (V ) DD1 2 Core Supply Voltage (V DD2 3 Input Voltage 4 Input Voltage on any 5V Tolerant I/O pins 5 Continuous Current at digital outputs 6 Package power dissipation ...
Page 27
Preliminary Information AC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated. ss Characteristics 1 CMOS Threshold 2 CMOS Rise/Fall Threshold Voltage High 3 CMOS Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating ...
Page 28
MT93L00A F0i t C4i Rout/Sout Bit 0, Channel 31 Rin/Sin Bit 0, Channel 31 Figure 9 - ST-BUS Timing at 2.048 Mb/s F0i t FPS C4i Sout/Rout Bit 7, Channel 31) Sin/Rin Bit 7, Channel 31) Figure 10 - GCI ...
Page 29
Preliminary Information AC Electrical Characteristics Characteristic 1 Master Clock Frequency, - Fsel = 0 - Fsel = 1 2 Master Clock Low 3 Master Clock High † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are ...
Page 30
MT93L00A AC Electrical Characteristics Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS ...
Page 31
... Preliminary Information Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard MS-026 MT93L00AB 100-Pin LQFP - B Suffix 100-Pin Dim Min Max A - 0.063 (1.60) A1 0.002 0.006 (0.05) (0.15) A2 0.053 0.057 (1.35) (1.45) b 0.007 0.011 (0.17) (0.27) D 0.630 (16.00 BSC) D1 0.551 (14.00 BSC) e 0.020 (0.50 BSC) E 0.630 (16.00 BSC) E1 0.551 (14.00 BSC) ...
Page 32
MT93L00A Pin #1 Corner 1.215 REF 15.00 0.20 R0.25 Typ. 0.54 ...
Page 33
...
Page 34
...
Page 35
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...