MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 22

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

22
MT93L00A
Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: 15h + Base Address
Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address: 35h + Base Address
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear
value defaults to 4800h= 0.5625 or -5dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and
the low byte is in Register 1.
Echo Canceller A, Adaptation Step Size (MU) Register 2
Echo Canceller B, Adaptation Step Size (MU) Register 2
Echo Canceller A, Non-Linear Processor Threshold Register 2 Read/Write Address: 19h + Base Address
Echo Canceller B, Non-Linear Processor Threshold Register 2 Read/Write Address: 39h + Base Address
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2’s
complement linear value defaults to 0B60h = 0.0889 or -21.0dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high
byte is in Register 2 and the low byte is in Register 1.
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to 4000h = 1.0
The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address: 14h + Base Address
Echo Canceller B, Double-Talk Detection Threshold Register 1 Read/Write Address: 34h + Base Address
Echo Canceller A, Adaptation Step Size (MU) Register 1
Echo Canceller B, Adaptation Step Size (MU) Register 1
Echo Canceller A, Non-Linear Processor Threshold Register 1 Read/Write Address: 18h + Base Address
Echo Canceller B, Non-Linear Processor Threshold Register 1 Read/Write Address: 38h + Base Address
NLP
DTDT
DTDT
NLP
MU
MU
7
7
7
7
7
15
7
15
7
7
15
7
NLP
NLP
MU
MU
DTDT
DTDT
6
6
6
6
6
14
14
6
6
6
14
6
NLP
NLP
MU
DTDT
MU
DTDT
5
5
5
5
13
13
5
5
5
5
5
13
NLP
NLP
MU
MU
4
4
DTDT
DTDT
4
4
12
12
4
4
4
4
4
12
NLP
NLP
MU
MU
3
3
DTDT
3
3
DTDT
11
3
11
3
3
3
11
NLP
3
NLP
MU
MU
2
2
2
2
10
DTDT
2
2
10
DTDT
2
2
NLP
2
10
NLP
MU
MU
1
1
1
1
9
9
DTDT
DTDT
1
1
1
1
NLP
NLP
9
1
MU
MU
0
0
0
0
8
8
0
0
DTDT
DTDT
0
0
Read/Write Address: 1Bh + Base Address
Read/Write Address: 3Bh + Base Address
Read/Write Address: 1Ah + Base Address
Read/Write Address: 3Ah + Base Address
(MU)
0
(NLPTHR)
(MU)
8
(NLPTHR)
(DTDT)
(DTDT)
Preliminary Information
Power Reset Value
Power Reset Value
Power Reset Value
Power Reset Value
Power Reset Value
Power Reset Value
48h
0Bh
40h
00h
60h
00h