MT93L04A Zarlink Semiconductor, MT93L04A Datasheet - Page 12

• Manufacturer Part Number: MT93L04A
• Manufacturer: Zarlink Semiconductor

MT93L04A
Pin Description (continued)
Fsel_d2
Step_d2
PLLVSS1_d2
PLLVDD_d2
PLLVSS2_d2
AT1_d2
DEVICE 3
TMS_d3
TDI_d3
TDO_d3
TCK_d3
TRSTB_d3
Test_En_d3
RESETB_d3
12
Halt_d2
Signal Name
Signal
ICO
ICO
Power
Power
Power
NC
Signal
Signal
Signal
Signal
Signal
ICO
Signal
Signal Type
BGA Ball #
W13
W14
W15
V13
Y14
Y15
V14
W1
W2
V2
Y1
U3
V3
T3
Frequency select (Input). This input selects the
Master Clock frequency operation. When Fsel pin
is low, nominal 19.2MHz Master Clock input must
be applied. When Fsel pin is high, nominal
9.6MHz Master Clock input must be applied.
Internal Connection. Connected to VSS for
normal operation
Internal Connection. Connected to VSS for
normal operation
PLL Ground. Must be connected to VSS
PLL Power Supply. Must be connected to VDD2
PLL Ground. Must be connected to VSS
No connection. The pin must be left open for
normal operation.
Test Mode Select (3.3V Input). JTAG signal that
controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data In (3.3V Input). JTAG serial test
instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data Out (Output). JTAG serial data
is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when
JTAG scan is not enabled.
Test Clock (3.3V Input). Provides the clock to the
JTAG test logic.
Test Reset (3.3V Input). Asynchronously
initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be
pulsed low on power-up or held low, to ensure that
the MT93L00 is in the normal functional mode.
This pin is pulled by an internal pull-down when
not driven.
Internal Connection. Connected to VSS for
normal operation
Device Reset (Schmitt Trigger Input). An active
low resets the device and puts the MT93L00 into a
low-power stand-by mode.
When the RESET pin is returned to logic high
and a clock is applied to the MCLK pin, the
device will automatically execute initialization
routines, which preset all the Control and Status
Registers to their default power-up values.
Signal Description
Preliminary Information