MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet
MT93L04AG
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MT93L04AG Summary of contents
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... The MT93L04 supports ITU-T G.165 and G.164 tone disable requirements. MT93L00 MT93L00 1 4 MT93L00 MT93L00 3 2 MT93L04A Preliminary Information ISSUE 2 September 2001 Ordering Information MT93L04AG 365 Ball BGA +85 C conforming to ITU-T or any combination of the G.168 two 1 ...
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MT93L04A V DD1 (3.3V) Rin Serial to Parallel Sin MCLK Fsel PLL C4i Timing F0i Unit DS CS R/W A10-A0 DTA Figure 1 - Functional Block Diagram for single MT93L00 (32 channels) Features of Single MT93L00 • Independent multiple channels ...
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Preliminary Information FOIB_d1 Tsig(12)_d1 Tsig(7)_d1 SC_in_d1 A Rout_d1 SC_Fclk_d1 SM_mclk_d1 Tsig(15)_d1 SC_set_d1 SC_reset_d1 B ST_mclk_d1 Sin_d1 Tsig(11)_d1 TM2_d1 Tsig(9)_d1 SC_en_d1 C C4IB Tsig(8)_d1 Tsig(13)_d1 A(2)_d1 Fsel_d1 Tsig(10)_d1 ...
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MT93L04A Pin Description Signal Name Signal Type V = 3.3V Power R6, R8, R13, R15, N15,H15, DD1 V = 1.8V Power DD2 VSS Power DEVICE 1 TMS_d1 User Signal TDI_d1 User Signal TDO_d1 User Signal TCK_d1 User Signal TRSTB_d1 User ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type IRQB_d1 User Signal DSB_d1 User Signal CSB_d1 User Signal R/WB_d1 User Signal DTAB_d1 User Signal D(0)_d1 User Signal D(1)_d1 User Signal D(2)_d1 User Signal D(3)_d1 User Signal D(4)_d1 User Signal D(5)_d1 ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Tsig(0)_d1 NC Tsig(1)_d1 NC Tsig(2)_d1 NC Tsig(3)_d1 NC Tsig(4)_d1 NC Tsig(5)_d1 NC Tsig(6)_d1 NC Tsig(7)_d1 NC ODE_d1 User Signal Sout_d1 User Signal Rout_d1 User Signal Sin_d1 User Signal Rin_d1 User Signal FOIb_d1 ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type SC_set_d1 ICO SM_mclk_d1 ICO ST_mclk_d1 ICO SC_en_d1 ICO SC_In_d1 ICO SC_Reset:_d1 ICO SC_Fclk_d1 ICO Tsig(8)_d1 NC Tsig(9)_d1 NC Tsig(10)_d1 NC Tsig(11)_d1 NC Tsig(12)_d1 NC Tsig(13)_d1 NC Tsig(14)_d1 NC Tsig(15)_d1 NC Tm1_d1 ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Fsel_d1 User Signal Halt_d1 ICO Step_d1 ICO PLLVSS1_d1 Power PLLVDD_d1 Power PLLVSS2_d1 Power AT1_d1 NC DEVICE 2 TMS_d2 Signal TDI_d2 Signal TDO_d2 Signal TCK_d2 Signal TRSTB_d2 Signal Test_En_d2 ICO RESETB_d2 Signal 8 ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type IRQB_d2 Signal DSB_d2 Signal CSB_d2 Signal R/WB_d2 Signal DTAB_d2 Signal D(0)_d2 Signal D(1)_d2 Signal D(2)_d2 Signal D(3)_d2 Signal D(4)_d2 Signal D(5)_d2 Signal D(6)_d2 Signal D(7)_d2 Signal A(0)_d2 Signal A(1)_d2 Signal A(2)_d2 ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Tsig(0)_d2 NC Tsig(1)_d2 NC Tsig(2)_d2 NC Tsig(3)_d2 NC Tsig(4)_d2 NC Tsig(5)_d2 NC Tsig(6)_d2 NC Tsig(7)_d2 NC ODE_d2 Signal Sout_d2 Signal Rout_d2 Signal Sin_d2 Signal Rin_d2 Signal FOIb_d2 Signal C4IB_d2 Signal 10 BGA ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type SC_set_d2 ICO SM_mclk_d2 ICO ST_mclk_d2 ICO SC_en_d2 ICO SC_In_d2 ICO SC_Reset:_d2 ICO SC_Fclk_d2 ICO Tsig(8)_d2 NC Tsig(9)_d2 NC Tsig(10)_d2 NC Tsig(11)_d2 NC Tsig(12)_d2 NC Tsig(13)_d2 NC Tsig(14)_d2 NC Tsig(15)_d2 NC Tm1_d2 ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Fsel_d2 Signal Halt_d2 ICO Step_d2 ICO PLLVSS1_d2 Power PLLVDD_d2 Power PLLVSS2_d2 Power AT1_d2 NC DEVICE 3 TMS_d3 Signal TDI_d3 Signal TDO_d3 Signal TCK_d3 Signal TRSTB_d3 Signal Test_En_d3 ICO RESETB_d3 Signal 12 BGA ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type IRQB_d3 Signal DSB_d3 Signal CSB_d3 Signal R/WB_d3 Signal B_d3 Signal D(0)_d3 Signal D(1) _d3 Signal D(2)_d3 Signal D(3)_d3 Signal D(4)_d3 Signal D(5)_d3 Signal D(6)_d3 Signal D(7)_d3 Signal A(0)_d3 Signal A(1)_d3 Signal ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Tsig(0)_d3 NC Tsig(1)_d3 NC Tsig(2)_d3 NC Tsig(3)_d3 NC Tsig(4)_d3 NC Tsig(5)_d3 NC Tsig(6)_d3 NC Tsig(7)_d3 NC ODE_d3 Signal Sout_d3 Signal Rout_d3 Signal Sin_d3 Signal Rin_d3 Signal FOIb_d3 Signal C4IB_d3 Signal 14 BGA ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type SC_set_d3 ICO SM_mclk_d3 ICO ST_mclk_d3 ICO SC_en_d3 ICO SC_In_d3 ICO SC_Reset:_d3 ICO SC_Fclk_d3 ICO Tsig(8)_d3 NC Tsig(9)_d3 NC Tsig(10)_d3 NC Tsig(11)_d3 NC Tsig(12)_d3 NC Tsig(13)_d3 NC Tsig(14)_d3 NC Tsig(15)_d3 NC Tm1_d3 ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Fsel_d3 Signal T12 Halt_d3 ICO Y13 Step_d3 ICO T11 PLLVSS1_d3 Power Y12 PLLVDD_d3 Power W12 PLLVSS2_d3 Power V12 AT1_d3 NC U12 DEVICE 4 TMS_d4 Signal E16 TDI_d4 Signal D17 TDO_d4 Signal C18 ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type IRQB_d4 Signal G17 DSB_d4 Signal H16 CSB_d4 Signal K16 R/WB_d4 Signal H17 DTAB_d4 Signal K17 D(0)_d4 Signal K18 D(1)_d4 Signal J16 D(2)_d4 Signal K19 D(3)_d4 Signal K20 D(4)_d4 Signal J20 D(5)_d4 ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Tsig(0)_d4 NC D19 Tsig(1)_d4 NC C20 Tsig(2)_d4 NC B20 Tsig(3)_d4 NC C19 Tsig(4)_d4 NC D18 Tsig(5)_d4 NC C17 Tsig(6)_d4 NC B19 Tsig(7)_d4 NC A20 ODE_d4 Signal B18 Sout_d4 Signal A19 Rout_d4 Signal ...
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Preliminary Information Pin Description (continued) Signal Name Signal Type SC_set_d4 ICO A17 SM_mclk_d4 ICO A16 ST_mclk_d4 ICO B15 SC_en_d4 ICO C14 SC_In_d4 ICO A15 SC_Reset:_d4 ICO B14 SC_Fclk_d4 ICO A14 Tsig(8)_d4 NC C13 Tsig(9)_d4 NC D12 Tsig(10)_d4 NC A12 Tsig(11)_d4 ...
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MT93L04A Pin Description (continued) Signal Name Signal Type Fsel_d4 Signal A11 Halt_d4 ICO E13 Step_d4 ICO D14 PLLVSS1_d4 Power E14 PLLVDD_d4 Power D15 PLLVSS2_d4 Power D16 AT1_d4 NC E15 DESCRIPTION OF THE SINGLE MT93L00 Device Overview The MT93L00 architecture contains ...
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Preliminary Information m/A-Law/ Sin Linear (channel N) Disable Tone Detector Programmable ST-BUS Bypass PORT2 Instability Detector Linear/ Rout m/A-Law (channel N) Figure 3 - Echo Canceller Functional Block Diagram Adaptive Filter The adaptive filter adapts to the echo path and ...
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MT93L04A In some applications the return loss can be higher or lower than 6dB. The MT93L00 allows the user to change the detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value ...
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Preliminary Information The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register A1/B1. It should be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP ...
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MT93L04A is activated by setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the interrupts and poll the TD bits in the Status Registers. Following the detection of a ...
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Preliminary Information with ECB contains undefined data. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo cancellation is required. Back-to-Back configuration is selected by writing “1” into the BBM bit of both Control Register A1 and Control Register ...
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MT93L04A channel A Sin + - echo path A Adaptive Filter (64ms) channel A Rout PORT2 Optional -12dB pad E.C.A channel echo Adaptive path B Filter (64ms) channel B Optional -12dB pad E.C.B a) Normal Configuration (64ms) ...
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Preliminary Information Enable Adaptation In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller to model the echo return path characteristics in order to cancel echo. This is the normal operating state. The echo ...
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MT93L04A Base Echo Canceller A Addr + 00h Control Reg A1 Control Reg 2 01h Status Reg 02h Reserved 03h Flat Delay Reg 04h Reserved 05h Decay Step Size Reg 06h Decay Step Number 07h Control Reg A3 08h Control ...
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Preliminary Information Normal Configuration For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B, channels 2 and 3 are active. Group ...
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MT93L04A Power Up Sequence On power up, the RESET pin must be held low for 100 s. Forcing the RESET pin low will put the MT93L00 in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, ...
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Preliminary Information All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin ...
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MT93L04A Test Data Registers As specified in IEEE 1149.1, the MT93L00 JTAG Interface contains three test data registers: • Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary ...
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Preliminary Information Register Descriptions (continued) Echo Canceller A, Control Register Reset INJDis BBM PAD Bypass Echo Canceller B, Control Register Reset INJDis BBM PAD Bypass Bit Name 0 ...
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MT93L04A Echo Canceller A, Control Register A2 Echo Canceller B, Control Register TDis PHDis NLPDis AutoTD NBDis Bit Name 2 HPFDis When high, the offset nulling high pass filters are bypassed in the Rin ...
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Preliminary Information Echo Canceller A, Flat Delay Register (FD) Echo Canceller B, Flat Delay Register (FD FD7 FD6 FD5 FD4 Echo Canceller A, Decay Step Number Register (NS) Echo Canceller B, Decay Step Number Register (NS) ...
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MT93L04A SSC Decay Step Size Control This register controls the step size (SS used during the exponential : 2-0 decay of MU. The decay rate is defined as a decrease factor of 2 every ...
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Preliminary Information Echo Canceller A, Noise Scaling (NS) Echo Canceller B, Noise Scaling (NS NS7 NS6 NS5 NS4 If the comfort noise level estimator is unable to correctly match the background noise level, this register can ...
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MT93L04A Echo Canceller A, Sin Peak Detect Register 2 (SP) Echo Canceller B, Sin Peak Detect Register 2 (SP SP15 SP14 SP13 SP12 Echo Canceller A, Sin Peak Detect Register 1 (SP) Echo Canceller B, Sin ...
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Preliminary Information Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address DTDT15 DTDT14 DTDT13 DTDT12 Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address: Echo ...
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MT93L04A Main Control Register 0 (EC group WR_all ODE MIRQ MTDBI MTDAI Bit Name 7 WR_all Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000h to 0003Fh which ...
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Preliminary Information Bit Name 7-5 unused Unused Bits. 4 MTDBI Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register ...
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MT93L04A Test Register res res res res res Bit Name 7:1 res Reserved bits. Must always be set to zero for normal operation. 0 Tirq Test IRQ: Useful for the application engineer to verify the ...
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Preliminary Information DC Electrical Characteristics Characteristics 1 Static Supply Current*** IDD_IO (VDD1=3.3V)*** (single device) IDD_CORE (single device) (VDD2 =1.8V)*** I 2 Total Power Consumption N for all 4 devices Input High Voltage S 4 Input Low ...
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MT93L04A AC Electrical Characteristics Characteristic 1 Frame pulse width (ST-BUS, GCI) 2 Frame Pulse Setup time before C4i falling (ST-BUS or GCI) 3 Frame Pulse Hold Time from C4i falling (ST-BUS or GCI) 4 C4i Period 5 C4i Pulse Width ...
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Preliminary Information t FPW F0i t FPS C4i t SOD Sout/Rout Bit 7, Channel 31) Sin/Rin Bit 7, Channel 31) Figure 10 - GCI Interface Timing at 2.048 Mb/s ODE Sout/Rout Figure 11 - Output Driver Enable (ODE) AC Electrical ...
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MT93L04A MCLK AC Electrical Characteristics Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after ...
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Preliminary Information DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 13 - Motorola Non-Multiplexed Bus Timing t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t ...
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... 4.00" 45’ (4X) 24.00 REF 1.17 (0.56) Seating Plane 1.00 (3X) REF. Ø 24.13 27.00 0.20 0.50 ~ 0.70 MT93L04AG 365 -Ball BGA Preliminary Information 0.60 ~ 0.90 (365X 1.27 0.15 2.33 0.13 ...
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