MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 26

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

MT93L04A
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back -to -Back configurations, MuteR and MuteS bits of Echo Canceller B must
always be “0”. Refer to Figure 3 and to Control Register 2 for bit description.
Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125 s) in order to properly clear the filter.
Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value.
The adaptation process is halted, however, the echo canceller continues to cancel echo.
26
PORT2
(quiet code)
echo
path B
Rout
echo
path A
Sin
+Zero
channel B
a) Normal Configuration (64ms)
channel A
channel B
channel A
E.C.A
E.C.B
2’s complement
LINEAR
Filter (64ms)
16 bits
Filter (64ms)
Adaptive
0000h
Adaptive
-
-
Optional -12dB pad
Optional -12dB pad
+
+
Table 1 - Quiet PCM Code Assignment
Figure 5 - Device configuration
MAGNITUDE
A-Law
SIGN/
PORT1
-Law
80h
Sout
Rin
PORT2
Rout
echo
path
Sin
echo
path A
PORT2
Rout
Sin
b) Extended Delay Configuration (128ms)
c) Back-to-Back Configuration (64ms)
E.C.A
Filter (64ms)
Adaptive
Optional -12dB pad
-
channel A
channel A
+
E.C.A
-Law
FFh
Optional -12dB pad
Preliminary Information
CCITT (G.711)
Adaptive Filter
(128 ms)
-
Optional -12dB pad
+
Filter (64ms)
Adaptive
E.C.B
+
-
A-Law
D5h
PORT1
echo
path
PORT1
Sout
Rin
Sout
Rin