MT93L16AQ Zarlink Semiconductor, MT93L16AQ Datasheet - Page 10

• Manufacturer Part Number: MT93L16AQ
• Description: Description = Low Voltage (3.3V) Acoustic Echo CANceller For Hands-free Applications ;; Package Type = Qsop ;; No. Of Pins = 36
• Manufacturer: Zarlink Semiconductor

MT93L16
Microport
The serial microport provides access to all MT93L16
internal read and write registers, plus write-only
access to the bootloadable program RAM (see next
section for bootload description.) This microport is
compatible with Intel MCS-51 (mode 0), Motorola
SPI
Semiconductor
microport consists of a transmit/receive data pin
(DATA1), a receive data pin (DATA2), a chip select
pin (CS) and a synchronous data clock pin (SCLK).
The MT93L16 automatically adjusts its internal
timing and pin configuration to conform to Intel or
Motorola/National
dynamically senses the state of the SCLK pin each
time CS pin becomes active (i.e. high to low
transition). If SCLK pin is high during CS activation,
then Intel mode 0 timing is assumed. In this case
DATA1 pin is defined as a bi-directional (transmit/
receive)
disconnected. If SCLK is low during CS activation,
then Motorola/National timing is assumed and
DATA1 is defined as the data transmit pin while
DATA2 becomes the data receive pin. The MT93L16
supports Motorola half-duplex processor mode
(CPOL=0 and CPHA=0). This means that during a
write to the MT93L16, by the Motorola processor,
output data from the DATA1 pin must be ignored.
This also means that input data on the DATA2 pin is
ignored by the MT93L16 during a valid read by the
Motorola processor.
All data transfers through the microport are two bytes
long. This requires the transmission of a Command/
Address byte followed by the data byte to be written
to or read from the addressed register. CS must
remain low for the duration of this two-byte transfer.
As shown in Figures 8 and 9, the falling edge of CS
indicates to the MT93L16 that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
between the MT93L16 and the microcontroller. At the
end of the two-byte transfer, CS is brought high again
to terminate the session. The rising edge of CS will
tri-state the DATA1 pin. The DATA1 pin will remain tri-
stated as long as CS is high.
Intel processors utilize Least Significant Bit (LSB)
first transmission while Motorola/National processors
use Most Significant Bit (MSB) first transmission.
10
(CPOL=0,
serial
port
Microwire
requirements.
CPHA=0),
and
DATA2
specifications.
and
The
is
microport
internally
National
The
The
accommodates these two schemes for normal data
bytes. However, to ensure timely decoding of the
R/W and address information, the Command/
Address byte is defined differently for Intel and
Motorola/National operations. Refer to the relative
timing diagrams of Figure 8 and Figure 9. Receive
data bits are sampled on the rising edge of SCLK
while transmit data is clocked out on the falling edge
of SCLK. Detailed microport timing is shown in
Figure 14 and Figure 15.
Bootload Process and Execution from RAM
A bootloadable program RAM (BRAM) is available on
the MT93L16 to support factory-issued software
upgrades to the built-in algorithm. To make use of
this bootload feature, users must include 4096 X
8bits of memory in their microcontroller system (i.e.
external to the MT93L16), from which the MT93L16
can be bootloaded. Registers and program data are
loaded into the MT93L16 in the same fashion via the
serial microport. Both employ the same command /
address / data byte specification described in the
previous section on serial microport. Either intel or
motorola mode may be transparently used for
bootloading. There are also two registers relevant to
bootloading (BRC=control and SIG=signature, see
Register Summary). The effect of these register
values on device operation is summarized in Table 5.
Bootload mode is entered and exited by writing to the
bootload bit in the Bootload RAM Control (BRC)
register
During bootload mode, any serial microport "write"
(R/W command bit =0) to an address other than that
of the BRC register
program BRAM. Call these transactions "BRAM-fill"
writes. Although a command/address byte must still
precede each data byte (as described for the serial
microport), the values of the address fields for these
"BRAM-fill" writes are ignored (except for the value
3fh, which designates the BRC register.) Instead,
addresses are internally generated by the MT93L16
for each "BRAM-fill" write. Address generation for
"BRAM-fill" writes resumes where it left off following
any read transaction while bootload mode is
enabled. The first 4096 such "BRAM-fill" writes while
bootload is enabled will load the memory, but further
ones after that are ignored.
the first 4096 bytes, the program BRAM will be filled.
Before bootload mode is disabled, it is recommended
that users then read back the value from the
signature register (SIG) and compare it to the one
supplied by the factory along with the code. Equality
verifies that the correct data has been loaded. The
signature calculation uses an 8-bit MISR which only
incorporates
MT93L16
at address 3fh (see Register Summary).
input
Preliminary Information
from
microport
will contribute to filling the
Following the write of
"BRAM-fill"
automatically
writes.