MT93L04 Zarlink Semiconductor, MT93L04 Datasheet
MT93L04
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MT93L04 Summary of contents
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... T1/E1/J1 multichannel echo cancellation • Wireless base stations Figure 1 - MT93L04 is MULTI-CHIP Module Consisting of 4 MT93L00 Devices Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2006, Zarlink Semiconductor Inc. All Rights Reserved. 128-Channel Voice Echo Canceller Ordering Information ...
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... MHz or 20 MHz master clock operation • 3.3 V pads and 1.8 V Logic core operation with 5-Volt tolerant inputs • No external memory required • Non-multiplexed microprocessor interface • IEEE-1149.1 (JTAG) Test Access Port MT93L04 V V DD2 (1.8V) SS Echo Canceller Pool Group 0 Group 1 Group 2 Group 3 ...
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... D(3)_d2 TD0_d2 DSB_d2 W Trstb_d2 PLLVDD_d2 D(0)_d2 PLLVSS1_d2 D(4)_d2 Tck_d2 Csb_d2 Y TDI_d2 RESETB_d2 D(1)_d2 corner is identified by metallized markings. MT93L04 Tsig(1)_d1 Fsel_d4 Tsig(14)_d4 A_IC2_d1 Tsig(0)_d1 SC_fclk_d4 Tsig(10)_d4 Tsig(2)_d1 DT1_d4 ...
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... User Signal TDI_d1 User Signal TDO_d1 User Signal TCK_d1 User Signal TRSTB_d1 User Signal Test_En_d1 ICO RESETB_d1 User Signal MT93L04 BGA Ball # Positive Power Supply. Nominally 3.3 volt I/O Voltage DD1 R9,R10,R11,R12,M15, Positive Power Supply. Nominally 1.8 volt. L15,K15,J15,F12,F11 Core Voltage DD2 F10,F9,J6, K6, L6,M6, Ground ...
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... A(8)_d1 User Signal A(9)_d1 User Signal A(10)_d1 User Signal MT93L04 BGA Ball # J5 Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. ...
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... ODE_d1 User Signal Sout_d1 User Signal Rout_d1 User Signal Sin_d1 User Signal Rin_d1 User Signal MT93L04 BGA Ball # E9 Internal Connection. Connected to VSS for normal operation A8 Internal Connection. Connected to VSS for normal operation A10 No connection. The pin must be left open for normal operation. ...
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... NC Tsig(14)_d1 NC Tsig(15)_d1 NC Tm1_d1 ICO Tm2_d1 ICO MT93L04 BGA Ball # A5 Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. C6 Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout) ...
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... TMS_d2 Signal TDI_d2 Signal TDO_d2 Signal TCK_d2 Signal TRSTB_d2 Signal MT93L04 BGA Ball # E4 Internal Connection. Connected to VSS for normal operation F3 No connection. The pin must be left open for normal operation. E2 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source ...
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... Signal D(4)_d2 Signal D(5)_d2 Signal D(6)_d2 Signal D(7)_d2 Signal MT93L04 BGA Ball # V5 Internal Connection. Connected to VSS for normal operation Y4 Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high ...
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... NC Tsig(1)_d2 NC Tsig(2)_d2 NC Tsig(3)_d2 NC Tsig(4)_d2 NC Tsig(5)_d2 NC Tsig(6)_d2 NC Tsig(7)_d2 NC ODE_d2 Signal MT93L04 BGA Ball # U9 V9 Address A0 to A10 (Input). These inputs provide W9 the A10 - A0 address lines to the internal Y9 registers. U10 T10 T9 V10 W10 U8 Y10 T8 Internal Connection. Connected to VSS for ...
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... ICO SC_Fclk_d2 ICO Tsig(8)_d2 NC Tsig(9)_d2 NC Tsig(10)_d2 NC MT93L04 BGA Ball # L1 Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. N4 Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2 ...
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... Power PLLVDD_d2 Power PLLVSS2_d2 Power AT1_d2 NC DEVICE 3 TMS_d3 Signal MT93L04 BGA Ball # R1 No connection. The pin must be left open for normal operation connection. The pin must be left open for normal operation connection. The pin must be left open for normal operation. ...
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... DSB_d3 Signal CSB_d3 Signal R/WB_d3 Signal B_d3 Signal MT93L04 BGA Ball # V13 Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Y14 Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK ...
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... Tsig(0)_d3 NC Tsig(1)_d3 NC Tsig(2)_d3 NC Tsig(3)_d3 NC Tsig(4)_d3 NC Tsig(5)_d3 NC Tsig(6)_d3 NC MT93L04 BGA Ball # W17 Y19 Data Bus (Bidirectional). These pins V16 form the 8-bit bidirectional data bus of the W18 microprocessor port. Y20 W19 V17 V18 U18 V19 Address A0 to A10 (Input) ...
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... ST_mclk_d3 ICO SC_en_d3 ICO SC_In_d3 ICO SC_Reset:_d3 ICO MT93L04 BGA Ball # M19 No connection. The pin must be left open for normal operation. M20 Output Drive Enable (Input). This input pin is logically AND’d with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled ...
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... Y13 Step_d3 ICO T11 PLLVSS1_d3 Power Y12 PLLVDD_d3 Power W12 MT93L04 BGA Ball # T17 Internal Connection. Connected to VSS for normal operation U17 No connection. The pin must be left open for normal operation. U16 No connection. The pin must be left open for normal operation. ...
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... F17 IRQB_d4 Signal G17 DSB_d4 Signal H16 MT93L04 BGA Ball # PLL Ground. Must be connected to VSS No connection. The pin must be left open for normal operation. Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven ...
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... ICO E18 Tsig(0)_d4 NC D19 Tsig(1)_d4 NC C20 MT93L04 BGA Ball # Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. Data Transfer Acknowledgment (Open Drain Output) ...
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... Signal B16 C4IB_d4 Signal C15 SC_set_d4 ICO A17 MT93L04 BGA Ball # No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation ...
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... B13 Sg1_d4 ICO C11 DT1_d4 NC B11 MCLK_d4 Signal D13 MT93L04 BGA Ball # Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection ...
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... PLLVSS2_d4 Power D16 AT1_d4 NC E15 MT93L04 BGA Ball # Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. ...
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... PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding • Each echo canceller in the MT93L00 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. MT93L04 22 Zarlink Semiconductor Inc. Data Sheet ...
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... DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0. A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo return. During these periods, the adaptation process is slowed down but it is not halted. MT93L04 Non-Linear Offset + ...
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... This keeps the perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP. The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2. MT93L04 DTDT(hex) = hex(DTDT(dec) * 32768) where 0 < DTDT(dec) < 1 ...
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... Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the MT93L04 where 0 < NLPTHR < 1 ...
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... Canceller A and B). They can be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figure 6. Normal Configuration In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in Figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously. MT93L04 26 Zarlink Semiconductor Inc. Data Sheet ...
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... In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet code. MT93L04 27 Zarlink Semiconductor Inc. ...
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... Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame (125 µs) in order to properly clear the filter. Disable Adaptation When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The adaptation process is halted, however, the echo canceller continues to cancel echo. MT93L04 Sout Sin echo path A ...
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... Figure 9). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 10). MT93L04 29 Zarlink Semiconductor Inc ...
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... Figure 8 shows the memory map of the control/status register blocks for all echo cancellers. When Extended Delay or Back-to-Back configuration is selected, Control Register A1/B1 and Control Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section. MT93L04 Base Echo Canceller B ...
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... For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries don’t care data. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B (Channel 11) will carry don’t care data. MT93L04 Channel Group ...
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... Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section for description. MT93L04 Channel Ctrl/Stat Registers Group 0 ...
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... The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. MT93L04 PC =9* Nb_of_groups + 3. < ...
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... The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO. • Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. MT93L04 34 Zarlink Semiconductor Inc. Data Sheet when it is ...
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... When low, Echo Cancellers A and B of the same group operate independently. Note: Do not enable both Extended-Delay and BBM configurations at the same time. Control Register B1 bit reserved bit and should be written “0”. MT93L04 Read/Write Address ...
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... TD DTDet res res res Bit Name 7 res Reserved bit Logic high indicates the presence of a 2100 Hz tone. MT93L04 Read/Write Address: 01 Read/Write Address Reset Value: MuteS MuteR Description Read Address: Read Address Reset Value: TDG NB Description 36 Zarlink Semiconductor Inc ...
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... Tone detection status bit gated with the AutoTD bit. Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100 Hz tone Logic high indicates the presence of a narrow-band signal on Rin. MT93L04 Read Address: Read Address TDG ...
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... MU profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one tap is equivalent to 125 µs (64 ms/512 taps). MT93L04 ...
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... SD SD res Bit Name 7 0 Must be set to zero. MT93L04 - then MU=2 for the first 40 taps of the echo canceller FIR 7-0 ≤ normal mode and 0 ≤ FD 7-0 ). The start of the exponential decay is defined 2 Step Size (SS)] where 7-0 =4, then the exponential decay start value is 512 - [NS ...
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... IR7 IR6 IR5 IR4 The NLP ramps-in comfort noise during the initial background noise estimation stage. This register provides control over the ramp-in speed. Higher values will increase the ramp-in speed. MT93L04 Read/Write Address: 09 Read/Write Address res res Reset Value: ...
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... These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. MT93L04 Read Address: Read Address: ...
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... Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register 10 Main Control Register 11 Main Control Register 12 Main Control Register 13 Main Control Register 14 Main Control Register 15 MT93L04 Read Address: Read Address SP11 SP10 SP9 SP8 ...
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... This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear value defaults to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1. MT93L04 Read Address: Read Address: ...
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... Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000h to 0003Fh which is Group 0 address mapping. Useful to initialize the 16 Groups of Echo Cancellers as per Group 0. When low, address mapping is per Figure 8. Note: Only the Main Control Register 0 has the WR_all bit. MT93L04 ...
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... Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. MT93L04 Read/Write Address: 400 1 0 ...
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... Bit Name 7 IRQ Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that no interrupt is pending and the FIFO is empty. 6:5 0 Unused bits. Always zero MT93L04 Description Read Address Reset Value Description 46 Zarlink Semiconductor Inc ...
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... Input on any 5 V Tolerant I/O pins 5 Continuous Current at digital outputs 6 Package power dissipation 7 Storage temperature * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. MT93L04 Read Address Reset Value: Description ...
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... V and are for design aid only: not guaranteed and not subject to production testing. DD1 * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage ( The *** specifications are for 1 MT93L00 device of the Multi-chip module. MT93L04 - Voltages are with respect to ground (Vss) unless otherwise stated. ‡ Sym. ...
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... Characteristics are over recommended operating conditions unless otherwise stated ° ‡ Typical figures are =3.3 V and for design aid only: not guaranteed and not subject to production testing DD1 * Note1: High Impedance is measured by pulling to the appropriate rail with R MT93L04 Sym. Level V 0.5V TT DD1 V 0 ...
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... C4i t SOD Sout/Rout Bit 7, Channel 31) Bit 0, Channel 0 t SIS Sin/Rin Bit 7, Channel 31) Bit 0, Channel 0 Figure 10 - GCI Interface Timing at 2.048 Mb/s ODE Sout/Rout Figure 11 - Output Driver Enable (ODE) MT93L04 Bit 6, Channel 0 Bit 5, Channel SIS SIH Bit 7, Channel 0 Bit 6, Channel 0 ...
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... Characteristics are over recommended operating conditions unless otherwise stated ° ‡ Typical figures are =3.3V and for design aid only: not guaranteed and not subject to production testing DD1 MCLK MT93L04 - Voltages are with respect to ground (V ‡ Sym. Min. Typ. Max. ...
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... Typical figures are =3.3 V and for design aid only: not guaranteed and not subject to production testing DD1 *Note 1:High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. MT93L04 ‡ Sym. Min. Typ. Max. ...
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... DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 13 - Motorola Non-Multiplexed Bus Timing MT93L04 t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD 53 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR V TT ...
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... ° 1.17 (0.56) Seating Plane C MT93L04 1.00 (3X) REF. Ø 24.13 27.00 ± 0.20 0.50 ~ 0.70 MT93L04AG 365 -Ball BGA 54 Zarlink Semiconductor Inc. Data Sheet 0.60 ~ 0.90 (365X 1.27 0.15 2.33 ± 0.13 ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...