MT93L04 Zarlink Semiconductor, MT93L04 Datasheet - Page 39

• Manufacturer Part Number: MT93L04
• Description: 128-channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

FD
is defined as FD
filter. The valid range of FD
default value of FD
SSC
of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4
x2
value of SSC
decay of MU where each step has a period of SS taps (see SSC
as:
Filter Length (512 or 1024) - [Decay Step Number (NS
For example, if NS
(4x2
SSC
7-0
7-4
Bit
Bit
3
2
1
0
7
4
res
2-0
0
7
7
)] = 256 taps for a filter length of 512 taps.
2-0
Echo Canceller A, Control Register A3
Echo Canceller B, Control Register B3
Echo Canceller A, Control Register A4
Echo Canceller B, Control Register B4
. For example; If SSC
Flat Delay
Decay Step Size Control
SD
res
6
6
2
2-0
PathDet
RingClr
PathClr
Name
Name
res
res
7-0
is 04h.NS
SD
0
res
5
5
:
7-0
This register defines the flat delay of the MU profile, (i.e., where the MU value is 2
7-0
1
x 8 taps. For example; if FD
=4 and SSC
is zero.
SD
res
4
4
0
7-0
Reserved bits. Must always be set to zero for normal operation.
When high, the instability detector is activated. When low, the instability detector is
disabled
When high, the current echo channel estimate will be cleared and the echo canceller
will enter fast convergence mode upon detection of a path change. When low, the
echo canceller will keep the current path estimate but revert to fast convergence
mode upon detection of a path change. Note: this bit is ignored if PathDet is low.
When high, the path change detector is activated. When low, the path change
detector is disabled.
Reserved bit. Must always be set to zero for normal operation.
Must be set to zero.
7-0
RingClr
Decay Step Number: This register defines the number of steps to be used for the
2-0
res
is: 0 ≤ FD
3
3
:
= 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default
This register controls the step size (SS) to be used during the exponential decay
2-0
PathClr
res
=4, then the exponential decay start value is 512 - [NS
2
2
7-0
PathDet
≤ 64 in normal mode and 0 ≤ FD
res
1
1
Zarlink Semiconductor Inc.
7-0
res
res
MT93L04
0
0
= 5, then MU=2
7-0
39
) x Step Size (SS)] where SS = 4 x2
Read/Write Address: 08
Read/Write Address: 28
Reset Value:
Read/Write Address: 09
Read/Write Address: 29
Reset Value:
Description
Description
2-0
-16
). The start of the exponential decay is defined
for the first 40 taps of the echo canceller FIR
7-0
≤ 128 in extended-delay mode. The
0A
50
H
H
H
H
H
H
.
+ Base Address
+ Base Address
+ Base Address
+ Base Address
.
SSC
7-0
x SS] = 512 - [4 x
2-0
.
-16
Data Sheet
). The delay