ADC08D1000QML National Semiconductor, ADC08D1000QML Datasheet
ADC08D1000QML
Related parts for ADC08D1000QML
ADC08D1000QML Summary of contents
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... Military (-55°C T This part will work in a radiation environment, with ex- cellent results, provided the guidelines in applications section 2.1 are followed. © 2009 National Semiconductor Corporation www.DataSheet.in ADC08D1000QML Features ■ Total Ionizing Dose ■ Single Event Latch-Up ■ Internal Sample-and-Hold ■ ...
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Block Diagram www.national.com www.DataSheet.in 2 ...
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Ordering Information NS Part Number ADC08D1000WGFQV Pin Configuration * Bottom of package must be soldered to ground plane to ensure rated performance. www.DataSheet.in SMD Part Number NS Package Number 5962F0520601VZC EM128A 300 krad(Si) 3 Package Description 128L, CERQUAD GULLWING 20180201 ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol 3 OutV / SCLK OutEdge / DDR / 4 SDATA 15 DCLK_RST PDQ 30 CAL 14 FSR/ECE CalDly / DES / 127 SCS www.national.com www.DataSheet.in Equivalent Circuit ...
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Pin Functions Pin No. Symbol 18 CLK+ 19 CLK I− Q− CMO 126 CalRun R 32 EXT 34 Tdiode_P ...
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Pin Functions Pin No. Symbol DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− / DQ5− DI5+ / ...
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Pin Functions Pin No. Symbol 42, 53, 64, 74, 87, 97, DR GND 108, 119 52, 63, 98, NC 109, 120 www.DataSheet.in Equivalent Circuit Ground return for V No Connection. Make no connection to these pins. 7 Description . DR ...
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Absolute Maximum Ratings (Note 1, Note 2) Supply Voltage ( Voltage on Any Input Pin Voltage (Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any ...
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ADC08D1000 Converter Electrical Characteristics DC Parameters The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Non-Extended Control Mode, SDR Mode, R limits apply for T = ...
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Symbol Parameter POWER SUPPLY CHARACTERISTICS I Analog Supply Current A Output Driver Supply I DR Current P Power Consumption D www.national.com www.DataSheet.in Conditions Notes PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High ...
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AC Parameters The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Non-Extended Control Mode, SDR Mode, R limits apply for ...
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Typical Electrical Characteristics DC Parameters The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Non-Extended Control Mode, SDR Mode, R Note 6) Symbol Parameters STATIC CONVERTER ...
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Symbol Parameters ANALOG OUTPUT CHARACTERISTICS V V input threshold to set DC CMO_LVL CMO Coupling mode Common Mode Output Voltage TC V CMO Temperature Coefficient C V Maximum V load Capacitance LOAD CMO CMO Bandgap Reference Voltage ...
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Typical Electrical Characteristics (Continued) AC Parameters The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Non-Extended Control Mode, SDR Mode, R Note 6) Symbol Parameters f ...
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Symbol Parameters Calibration delay determined by pin t CalDly 127 Low Calibration delay determined by pin t CalDly 127 High Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of ...
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Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig- nal and goes into the “hold” mode the aperture ...
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one- half the sampling frequency, ...
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Timing Diagrams www.national.com www.DataSheet.in FIGURE 3. ADC08D1000 Timing — SDR Clocking FIGURE 4. ADC08D1000 Timing — DDR Clocking 18 20180214 20180259 ...
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FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low www.DataSheet.in FIGURE 5. Serial Interface Timing FIGURE 6. Clock Reset Timing in DDR Mode 19 20180219 20180220 20180223 www.national.com ...
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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 9. Self Calibration and On-Command Calibration Timing FIGURE 10. For On-Command Calibration Only (See para. 2.1, The Cal Pin) 20 20180224 20180225 20180226 ...
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Typical Performance Characteristics INL vs CODE DNL vs. CODE POWER DISSIPATION vs. CLK FREQUENCY www.DataSheet. =1.9V, F =1000MHz CLK INL vs TEMPERATURE 20180264 DNL vs. TEMPERATURE 20180266 ENOB vs. CLOCK DUTY CYCLE 20180281 21 =25°C ...
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ENOB vs. TEMPERATURE ENOB vs. CLK FREQUENCY SNR vs. TEMPERATURE www.national.com www.DataSheet.in ENOB vs. SUPPLY VOLTAGE 20180276 ENOB vs. INPUT FREQUENCY 20180278 SNR vs. SUPPLY VOLTAGE 20180268 22 20180277 20180279 20180269 ...
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SNR vs. CLK FREQUENCY THD vs. TEMPERATURE THD vs. CLK FREQUENCY www.DataSheet.in SNR vs. INPUT FREQUENCY 20180270 THD vs. SUPPLY VOLTAGE 20180272 THD vs. INPUT FREQUENCY 20180274 23 20180271 20180273 20180275 www.national.com ...
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SFDR vs. TEMPERATURE SFDR vs. CLK FREQUENCY Spectral Response at FIN = 248 MHZ www.national.com www.DataSheet.in SFDR vs. SUPPLY VOLTAGE 20180285 SFDR vs. INPUT FREQUENCY 20180282 Spectral Response at FIN = 498 MHZ 20180287 24 20180284 20180283 20180288 ...
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CROSSTALK vs SOURCE FREQUENCY STEP RESPONSE www.DataSheet.in FULL POWER BANDWIDTH 20180263 STEP RESPONSE DETAIL VIEW 20180261 25 20180286 20180262 www.national.com ...
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Functional Description The ADC08D1000 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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The Analog Inputs The ADC08D1000 must be driven with a differential input sig- nal. Operation with a single-ended signal is not recommend- ed important that the input signals are either a.c. coupled to the inputs with the ...
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OutEdge Setting To help ease data capture in the SDR mode, the output data may be caused to transition on either the positive or the neg- ative edge of the output data clock (DCLK). This is chosen with the ...
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Feature SDR or DDR Clocking DDR Clock Phase SDR Data transitions with rising or falling DCLK edge LVDS output level Power-On Calibration Delay Full-Scale Range Input Offset Adjust Dual Edge Sampling Selection Dual Edge Sampling Input Channel Selection DES Sampling ...
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Subsequent register accesses may be performed immediate- ly, starting with the 33rd SCLK. This means that the SCS input does not have to be de-asserted and asserted again between register addresses possible, although not recommended, to keep the ...
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I-Channel Offset Addr: 2h (0010b) D15 D14 D13 D12 D11 (MSB) Offset Value Sign Bits 15:8 Offset Value. The input offset of the I-Channel ADC is adjusted linearly and monotonically by the value ...
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Addr: Dh (1101b) D15 D14 D13 DEN ACP Bit 15 DES Enable. Setting this bit to 1b enables the Dual Edge Sampling mode. In this mode the ADCs in this device are used ...
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... DCLK line during this reset event. When the DCLK_RST signal is de-asserted in synchronization with the CLK rising edge, the next CLK falling edge synchronizes the DCLK output with those of other ADC08D1000QMLs in the system. The DCLK output is enabled again after a constant delay (relative to the input clock frequency) which is equal to the CLK input to DCLK output delay (t exhibits this delay characteristic in normal operation ...
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The internal voltage divider resistors provide too little current to set the midpoint voltage reliably in radiation environments. The CAL pin should be kept at a logic ...
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If d.c. coupling is used best to servo the input common mode voltage, using the V pin, to maintain optimum per- CMO formance. An example of this type of circuit is shown in 13. FIGURE 13. Example of ...
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Electrical Characteristics Table. The low and high times of the input clock signal can affect the performance of any A/D Converter. The ADC08D1000 fea- tures a duty cycle ...
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FIGURE 16. ENOB vs. Junction Temperature, 749MHz input FIGURE 17. ENOB vs. Junction Temperature, 249MHz input 2.5.2.3 Calibration Delay The CalDly input (pin 127) is used to select one of two delay times after the application of power to the ...
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Power Down Feature The Power Down pins (PD and PDQ) allow the ADC08D1000 to be entirely powered down (PD) or the "Q" channel to be powered down and the "I" channel to remain active. See Sec- tion 1.1.7 for ...
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For reliability reasons, the die temper- ature should be kept to a maximum of 150°C. That is, T (ambient temperature) plus ADC power consumption times θ (junction to ...
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Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection to ground. This is because this path from the die to ground is a lower impedance than offered by the package ...
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Revision History Date Released Revision 01/29/07 A 05/07/07 B 05/28/09 C 11/09/09 D www.DataSheet.in Section New Product/ Data Sheet Initial Release General Description, Features, Key Specifications, Ordering Information Table, Absolute Maximum Ratings, Typical Electrical Characteristics, Functional Description, Note Absolute Maximum ...
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Physical Dimensions www.national.com www.DataSheet.in inches (millimeters) unless otherwise noted 128-Lead Ceramic Quad (Gold Lead Finish) NS Package Number EL128A 42 ...
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Notes 43 www.national.com ...
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