MT90823 Zarlink Semiconductor, MT90823 Datasheet
MT90823
Available stocks
Related parts for MT90823
MT90823 Summary of contents
Page 1
... F0i FE/ WFPS HCLK Description The MT90823 Large Digital Switch has a non-blocking switch capacity of: 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s; 1,024 x 1,024 channels at 4.096 Mb/s; and 512 x 512 channels at 2.048 Mb/s. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control ...
Page 2
... MT90823 STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK VDD 80 78 STi0 STi1 82 STi2 84 STi3 STi4 STi5 86 STi6 88 STi7 STi8 90 STi9 STi10 STi11 92 STi12 STi13 94 STi14 96 STi15 F0i 98 FE/HCLK ...
Page 3
... AD5 VDD AD2 AD3 VSS VDD AD0 VSS AD1 A6 R/W/RW AS/ALE VSS VSS A5 A7 DS/ CSTo 48 DTA D15 46 D14 D13 44 D12 D11 42 D10 VSS 38 VDD 36 AD7 AD6 34 AD5 AD4 AD3 32 AD2 30 AD1 AD0 28 VSS MT90823 3 ...
Page 4
... MT90823 Pin Description Pin # 84 100 100 PLCC MQFP LQFP 1, 11, 31, 41, 28, A1,A2,A12,A13, 30, 54 56, 66, 38, B1,B2,B7,B12, 64, 75 76, 99 53, B13,C3,C5,C7, 63, C9,C11,E3,E11 73, G3,G11,J3,J11, 96 L3,L5,L7,L9,L11, M1,M2,M12,M13 2, 32, 5, 40, 37, C4,C6,C8,C10 64,98 D3,D11,F3,F11, H3,H11,K3,K11, L4,L6,L8,L10 68- B6,A6,A5,B5,A4, 72 B4,A3, 81- C1,C2,D1,D2,E1 E2,F1,F2,G1,G2, H1,H2,J1,J2,K1 100 ...
Page 5
... N5 RESET Device Reset (5V Tolerant Input): This input (active LOW) puts the MT90823 in its reset state to clear the device internal counters, registers and bring STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply ...
Page 6
... N12 CS Chip Select (5V Tolerant Input): Active low input used by a microprocessor to activate the microprocessor port of MT90823. M11 AS/ALE Address Strobe or Latch Enable (5V Tolerant Input): This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non- multiplexed bus operation, connect this pin to ground ...
Page 7
... The serial input streams of the MT90823 can have a bit rate of 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125µs wide frames, which contain 32 128 channels, respectively. The data rates on input and output streams are identical. By using Mitel’ ...
Page 8
... MT90823 Functional Description A functional Block Diagram of the MT90823 is shown in Figure 1. Data and Connection Memory For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the data memory. Depending upon the selected operation programmed in the interface mode select (IMS) register, the useable data memory may be as large as 2,048 bytes ...
Page 9
... Data Sheet The MT90823 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the MT90823 is in ST-BUS/GCI mode. If the WFPS pin is high, the MT90823 is in the wide frame pulse (WFP) frame alignment mode. In ST-BUS/GCI mode, the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT90823 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI ...
Page 10
... See Figure 4, Table 11 and Table 12 for delay offset programming. Serial Input Frame Alignment Evaluation The MT90823 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the IMS register is changed from low to high ...
Page 11
... This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing connected to the MT90823. If DS/RD is high at the falling edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is low at the falling edge of AS/ALE, then the mode 2 multiplexed bus timing is selected. ...
Page 12
... Memory Mapping The address bus on the microprocessor interface selects the MT90823 internal registers and memory. If the A7 address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and frame input offset (FOR) registers are addressed shown in Table 4 ...
Page 13
... The loopback bit should be used for diagnostic purpose only; this bit should be set to zero for normal operation. If all LPBK bits are set high for all connection memory locations, the associated ST-BUS output channel data is internally looped back to the ST-BUS input channel (i.e., SToN channel m data loops back to STi N channel m). Zarlink Semiconductor Inc. MT90823 13 ...
Page 14
... MT90823 (Note ...
Page 15
... Data Sheet Initialization of the MT90823 During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the normal functional mode pull-down resistor can be connected to this pin so that the device will not enter the JTAG test mode during power up. ...
Page 16
... MT90823 Read/Write Address: Reset Value Bit Name 15-10 Unused Must be zero for normal operation. 9-5 BPD4-0 Block Programming Data. These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4- 0 are loaded into bit 15 to bit 11 of the connection memory ...
Page 17
... Frame Delay Bits. The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the SFE bit of the IMS register changes from (FD10 = MSB, FD0 = LSB) Zarlink Semiconductor Inc FD6 FD5 FD4 FD3 FD2 FD1 Description MT90823 1 0 FD0 17 ...
Page 18
... MT90823 ST-BUS Frame CLK Offset Value FE Input GCI Frame CLK Offset Value FE Input Figure 4 - Example for Frame Alignment Measurement (FD[10: (FD11 = 0, sample at CLK low phase Zarlink Semiconductor Inc. Data Sheet ...
Page 19
... Description Zarlink Semiconductor Inc OF10 DLE1 OF02 OF01 OF00 OF50 DLE5 OF42 OF41 OF40 OF90 DLE9 OF82 OF81 OF80 OF130 DLE13 OF122 OF121 OF120 MT90823 1 0 DLE0 0 DLE4 0 DLE8 0 DLE12 19 ...
Page 20
... MT90823 Input Stream Offset No clock period shift (Default) + 0.5 clock period shift +1.0 clock period shift +1.5 clock period shift +2.0 clock period shift +2.5 clock period shift +3.0 clock period shift +3.5 clock period shift +4.0 clock period shift +4.5 clock period shift Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) and Frame Delay Bits (FD11, FD2-0) ...
Page 21
... Table 13 - Connection Memory Bits CAB Bits Used to Determine the Source Channel of the Connection CAB4 to CAB0 (32 channel/input stream) CAB5 to CAB0 (64 channel/input stream) CAB6 to CAB0 (128 channel/input stream) Zarlink Semiconductor Inc CAB5 CAB4 CAB3 CAB2 CAB1 Description MT90823 1 0 CAB0 21 ...
Page 22
... The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. Test Access Port (TAP) The Test Access Port (TAP) provides access to the many test functions of the MT90823. It consists of three input pins and one output pin. The following pins comprise the TAP. • ...
Page 23
... The LSB bit in the device identification register is the first bit clocked out. The MT90823 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out. All tristate enable bits are active high. ...
Page 24
... MT90823 24 Boundary Scan Bit 0 to Bit 117 Output Device Pin Tristate Scan Control Cell STo7 0 1 STo6 2 3 STo5 4 5 STo4 6 7 STo3 8 9 STo2 10 11 STo1 12 13 STo0 14 15 ODE CSTo 17 18 DTA 19 D15 20 21 D14 23 24 D13 26 27 D12 ...
Page 25
... STo15 102 103 STo14 104 105 STo13 106 107 STo12 108 109 STo11 110 111 STo10 112 113 STo9 114 115 STo8 116 117 Zarlink Semiconductor Inc. MT90823 Input Scan Cell ...
Page 26
... Applications Switch Matrix Architectures The MT90823 is an ideal device for medium to large size switch matrices where voice and grouped data channels are transported within the same frame. In such applications, the voice samples have to be time interchanged with a minimum delay while maintain- ing the integrity of grouped data. To ensure the integrity of grouped data during switching and to provide a minimum delay for voice connections, the MT90823 provides per-channel selection between variable and constant throughput delay ...
Page 27
... HMVIP and MVIP-90 standard, the device can only operate with data rate of 2 Mb/s. Refer to the ST-BUS output delay parameter, t The MT90823 is designed to accept a common frame pulse F0i, the 4.096 MHz and 16.384 MHz clocks required by the HMVIP standards. To enable the Wide Frame Pulse Frame Alignment Mode, the WFPS pin has to be set to HIGH and the DR1 and DR0 bits set for 8 ...
Page 28
... Switch Matrix (Figure 6) 4,096 x 4,096 Switch Matrix (Figure 6) Figure 9 - 8,192 x 8,192 Channel Switch Matrix Zarlink Semiconductor Inc. Data Sheet 8,192 x 8,192 channel Switch Matrix Sixteen MT90823 (8 Mb/s mode) (See Figure 9) 32 Streams OUT 32 Streams ...
Page 29
... STi1 2 Mb/s (8.192 Mb/s per channel) Sym Min Max V -0 0.3 5 +125 S ) unless otherwise stated. ss Max Units Test Conditions +85 °C 3 400mV noise margin DD 5.5 V 0.3V V 400mV noise margin DD MT90823 Units °C 29 ...
Page 30
... MT90823 DC Electrical Characteristics - Characteristics Mb/s Supply Current @ Input High Voltage Input Low Voltage Input Leakage (input pins) S Input Leakage (with pull-up or pull- down) 5 Input Pin Capacitance 6 Output High Voltage O 7 Output Low Voltage High Impedance Leakage ...
Page 31
... HFPH t 190 300 HCP 85 150 t HCH 85 150 t HCL - DIF Zarlink Semiconductor Inc. MT90823 Units Notes ns WFPS Pin = WFPS Pin = 0 ns WFPS Pin = 0 ns WFPS Pin = WFPS Pin = WFPS Pin = ...
Page 32
... MT90823 AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic 1 Sti Set-up Time 2 Sti Hold Time 3 Sto Delay - Active to Active 4 STo delay - Active to High-Z 5 Sto delay - High-Z to Active 6 Output Driver Enable (ODE) Delay 7 CSTo Output Delay Note: 1. High Impedance is measured by pulling to the appropriate rail with R ...
Page 33
... Zarlink Semiconductor Inc Bit 2, Channel 0 Bit 2, Channel 0 t HCP t HCH Bit Bit Bit Bit MT90823 ...
Page 34
... MT90823 (ST-BUS or) (WFPS mode) (GCI mode) 34 CLK V CLK Valid Data HiZ STo t ZD HiZ Valid Data STo t XCD CSTo Figure 14 - Serial Output and External Control ODE t t ODE ODE Valid Data STo HiZ Figure 15 - Output Driver Enable (ODE) Zarlink Semiconductor Inc. ...
Page 35
... ALWR t 0 CSW t 20 DSW t SWD t 5 DHW t AKD @ 4Mb/s @ 8Mb/s t AKH , with timing corrected to cancel time taken to discharge C L Zarlink Semiconductor Inc. MT90823 Max Units Test Conditions =150pF =150pF Note ...
Page 36
... MT90823 t ALW ALE t ADS AD0-AD7 HiZ D8-D15 DTA 36 t ADH ADDRESS HiZ t ALRD t CSR t CSW t SWD t t ALWR DDR t AKD Figure 16 - Multiplexed Bus Timing (Mode 1) Zarlink Semiconductor Inc. Data Sheet HiZ DATA t CSRW DHR DHW t DSW t AKH V CT ...
Page 37
... DWS t SWD t 60 RWS t 5 RWH t 10 DHR t 10 DSH t AKD @ 4Mb/s @ 8Mb/s t AKH , with timing corrected to cancel time taken to discharge C L Zarlink Semiconductor Inc. MT90823 Max Units Test Conditions =150pF 122 =150pF Note 1 ...
Page 38
... MT90823 DS R/W AS AD0-AD7 HiZ D8-D15 WR AD0-AD7 D8-D15 HiZ RD CS DTA AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS rising 7 Data setup from DTA Low on Read ...
Page 39
... READ AD0-AD7 D8-D15 WRITE DTA Figure 18 - Motorola Non-Multiplexed Bus Timing t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t AKD Zarlink Semiconductor Inc. MT90823 CSH RWH ADH DHR DHW ...
Page 40
... MT90823 40 Zarlink Semiconductor Inc. Data Sheet ...
Page 41
...
Page 42
...
Page 43
... Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE ACN 213934 20Jan03 DATE APPRD. Package Code : GA Previous package codes: ...
Page 44
...
Page 45
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...