MT90823 Zarlink Semiconductor, MT90823 Datasheet - Page 27

• Manufacturer Part Number: MT90823
• Description: 3V Large Digital Switch
• Manufacturer: Zarlink Semiconductor

Data Sheet
Wide Frame Pulse (WFP) Frame Alignment Mode
When the device is in the wide frame pulse mode and if the input data streams are sampled at 3/4 bit time, the
device can operate in the HMVIP and MVIP-90 environment. When input data streams are sampled at half-bit time
as specified in the HMVIP and MVIP-90 standard, the device can only operate with data rate of 2 Mb/s. Refer to the
ST-BUS output delay parameter, t
The MT90823 is designed to accept a common frame pulse F0i, the 4.096 MHz and 16.384 MHz clocks required by
the HMVIP standards. To enable the Wide Frame Pulse Frame Alignment Mode, the WFPS pin has to be set to
HIGH and the DR1 and DR0 bits set for 8.192Mb/s data rate operation.
Digital Access Cross-Connect System
Figure 8 illustrates the use of MT90823 devices to construct a 256 E1/T1 Digital Access Cross- connect System
(DACS). The system consists of 32 trunk cards each having eight E1 or T1 trunk interfaces for a total of 256 trunks.
Each trunk card uses two MT8986 Multi-rate Digital Switches. The central switching block uses 16 MT90823
devices.
The block diagram at Figure 9 shows how an 8,192 x 8,192 channel switch can be constructed from 4,096 x 4,096
channel switch modules. Figure 6 shows the implementation of the individual 4,096 x 4,096 channel switch
modules from four MT90823 devices.
Figure 10 shows an eight-stream trunk card using MT8986 Multi-rate Digital Switches to concentrate 32-channel
2.048 Mb/s ST-BUS (DSTi and DSTo) streams at each E1/T1 trunk onto four 128-channel 8.192 Mb/s streams.
The DACS switching matrix that formerly required 256 MT8986 devices in a square (16 x 16) configuration can now
be provided by 64 MT8986 and 16 MT90823 devices (see Figure 8).
Note:
1. Use the external mux to select one of the serial frame pulses.
2. To start a measurement cycle, set the Start Frame Evaluation (SFE) bit in the IMS register low for at least 1 frame.
3. Frame evaluation starts when the SFE bit is changed from low to high.
4. Two frames later, the Complete Frame Evaluation (CFE) bit of the Frame Alignment Register (FAR) changes from low
to high to signal the CPU that a valid offset measurement is ready to be read from bit [11:0] of the FAR register.
5. The SFE bit must be set to zero before a new measurement cycle started.
Figure 7 - Serial Input Frame Alignment Evaluation for Various Frame Pulses
FP STi15
FP STi0
FP STi1
FP STi2
STi0
STi1
STi2
STi15
SOD
External
Mux
, as specified in the AC Electrical Characteristic table.
input
FE
Zarlink Semiconductor Inc.
Frame Alignment
Evaluation circuit
MT90823
CLK
FP
Timing Source
Central
STo[0:15]
MT90823
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