NJU6624C New Japan Radio, NJU6624C Datasheet - Page 17

• Manufacturer Part Number: NJU6624C
• Description: 14-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER with SMOOTH SCROLL FUNCTION
• Manufacturer: New Japan Radio

(m)Write Data to CG, DD or MK RAM
(m)Write Data to CG, DD or MK RAM
(n)Read Data Key
(n)Read Data Key
By the execution of this instruction, the binary 8-bit data (A
By the execution of this instruction, the binary 8-bit data (A
bit data (A
bit data (A
struction. After this instruction execution, the address increment (+1) or decrement(-1) is performed automatically
struction. After this instruction execution, the address increment (+1) or decrement(-1) is performed automatically
according to the entry mode set. And the display shift is also executed according to the previous entry mode set.
according to the entry mode set. And the display shift is also executed according to the previous entry mode set.
However, the data in MK RAM (1C)H and (1D)H are not displayed, bat the automatic address increment is per-
However, the data in MK RAM (1C)H and (1D)H are not displayed, bat the automatic address increment is per-
formed. And the display is not changed by the data written into MK RAM (1C)H and (1D)H
formed. And the display is not changed by the data written into MK RAM (1C)H and (1D)H
Read data key is a instruction for data reading out of keyscan. However, the bit 8 to 15 are input data. After this 8-
Read data key is a instruction for data reading out of keyscan. However, the bit 8 to 15 are input data. After this 8-
bit data were input, the operation change to output from input at the falling edge of 8th SCK clock.
bit data were input, the operation change to output from input at the falling edge of 8th SCK clock.
-Write Data to DD RAM
-Write Data to DD RAM
-Write Data to MK RAM
-Write Data to MK RAM
-Write Data to CG RAM
-Write Data to CG RAM
4 4
to A
to A
Code
Code
Code
Code
0 0
) are written into the CG or MK RAM. The selection of RAM is determined by the previous in-
) are written into the CG or MK RAM. The selection of RAM is determined by the previous in-
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13 D12 D11 D10 D9
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
7 7
to A
to A
D8
D8
D8
D8
0
0
0
1
0 0
) are written into the DD RAM, and the binary 5-
) are written into the DD RAM, and the binary 5-
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
KL3 KL2 KL1 KL0
D7
D7
D7
D7
*
*
D6
D6
D6
D6
*
*
D5
D5
D5
D5
*
*
DM4 DM3 DM2 DM1 DM0
DC4 DC3 DC2 DC1 DC0
D4
D4
D4
D4
NJU6624C
NJU6624C
D3
D3
D3
D3
0
KH2 KH1 KH0
D2
D2
D2
D2
D1
D1
D1
D1
D0
D0
D0
D0