L320MT90QI Advanced Micro Devices, L320MT90QI Datasheet - Page 21

• Manufacturer Part Number: L320MT90QI
• Description: 32 Megabit 2 M X 16-bit/4 M X 8-bit Mirrorbit 3.0 Volt-only Boot Sector Flash Memory - Advanced Micro Devices
• Manufacturer: Advanced Micro Devices

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables
for command definitions). In addition, the following
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
May 16, 2003
Figure 3. SecSi Sector Protect Verify
Write 40h to SecSi
Read from SecSi
Sector address
Sector address
A1 = 1, A0 = 0
A1 = 1, A0 = 0
Write 60h to
with A6 = 0,
any address
with A6 = 0,
RESET# =
V
Wait 1 s
START
IH
or V
ID
Remove V
SecSi Sector is
SecSi Sector is
If data = 00h,
If data = 01h,
from RESET#
Protect Verify
SecSi Sector
unprotected.
Write reset
protected.
command
complete
IH
or V
ID
12
D A T A S H E E T
and
Am29LV320MT/B
13
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during V
power-up and power-down transitions, or from system
noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V
system must provide the proper signals to the control
pins to prevent unintentional writes when V
greater than V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
given in Tables 8–11. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 8–11. The
system must write the reset command to return the de-
vice to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/flash/cfi. Al-
ternatively, contact an AMD representative for copies
of these documents.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
LKO
or WE# = V
.
IL
and OE# = V
LKO
CC
IH
, the device does not ac-
is greater than V
. To initiate a write cycle,
IH
during power up,
LKO
. The
CC
21
CC
CC
is