MC145426 Motorola, MC145426 Datasheet - Page 11

• Manufacturer Part Number: MC145426
• Description: (MC145422 / MC145426) UNIVERSAL DIGITAL-LOOP TRANSCEIVER(UDLT)
• Manufacturer: Motorola

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DataSheet
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Tx
Transmit Data Output
output on this pin on the rising edges of CLK while TE1 is
high and is high impedance when TE1 is low.
X1
Crystal Input
10 M resistor across X1 and X2 and 25 pF capacitors from
X1 and X2 to V SS are required for stability and to ensure
startup. X1 may be driven by an external CMOS clock signal
if X2 is left open.
X2
Crystal Output
15 pF of additional capacitance (see X1 pin description).
CLK
Clock Output
the data clock for the telset codec–filter. It is generated by di-
viding the oscillator down to 128 kHz and starts upon the
completion of demodulation of an incoming burst from the
master. At this time, CLK begins and TE1 goes high. CLK will
remain active for 16 periods, at the end of which it will remain
low until another transmission from the master is demodu-
lated. In this manner, sync from the master is established in
the slave and any clock slip between the master and the
slave is absorbed each frame. CLK is generated in response
to an incoming burst from the master, however, if TE is
brought high, then CLK and TE1/RE1 are generated from the
internal oscillator until TE is brought low or an incoming burst
from the master is received. CLK is disabled when LB is held
low.
Rx
Receive Data Input
on the first eight falling edges of CLK after RE1 goes high.
Mu/A
Tone Digital Format Input
wave tone, when TE is high, is Mu–Law (Mu/A = 1) or A–Law
(Mu/A = 0) format.
RE1
Receive Data Enable 1 Output
inverse of TE1 (see TE1 pin description).
LO1, LO2
Line Driver Outputs
modified DPSK bursts each frame and are push–pull. These
pins are driven to V ref when the device is not modulating.
MOTOROLA
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This is a standard B–series CMOS output. Voice data is
A 4.096 MHz crystal is tied between this pin and X2. A
This pin is capable of driving one external CMOS input and
This is a standard B–series CMOS output which provides
Voice data from the telset codec–filter is input on this pin
This pin determines if the PCM code of the 500 Hz square
This is a standard B–series CMOS output which is the
These outputs drive the twisted pair line with 256 kHz
ceiver ICs main application is to bidirectionally transmit the
digital signals present at a codec–filter digital–PABX back-
plane interface over normal telephone wire pairs. This allows
the remoting of the codec–filter in a digital telephone set and
enables each set to have a high speed data access to the
PABX switching facility. In effect, the UDLT allows each
PABX subscriber direct access to the inherent 64 kbps data
routing capabilities of the PABX.
64 kbits of voice data and 16 kbps of signaling data in two–
wire format over normal telephone pairs. The UDLT is a two–
chip set consisting of a master and a slave. The master
UDLT replaces the codec–filter and SLIC on the PABX line
card, and transmits and receives data over the wire pair to
the teleset. The UDLT appears to the linecard and backplane
as if it were a PCM Codec–Filter and has almost the same
digital interface features as the MC145500 series codec–fil-
ters. The slave UDLT is located in the telset and interfaces
the codec–filter to the wire pair. By hooking two UDLTs back–
to–back, a repeater can also be formed. The master and
slave UDLTs operate in a frame synchronous manner, sync
being established at the slave by the timing of the master’s
transmission. The master’s sync is derived from the PABX
frame sync.
voice data and two bits of signaling data are transmitted and
received each frame in a half–duplex manner (i.e., the slave
waits until the transmission from the master is completely re-
ceived before transmitting back to the master). Transmission
occurs at 256 kHz bit rate using a modified form of DPSK.
This “ping– pong” mode will allow transmission of data at dis-
tances up to two kilometers before turnaround delay be-
comes a problem. The UDLT is so defined as to allow this
data to be handled by the linecard, backplane, and PABX as
if it were just another voice conversation. This allows existing
PABX hardware and software to be unchanged and yet pro-
vides switched 64 kbps voice or data communications
throughout its service area by simply replacing a subscrib-
er’s linecard and teleset. A feature in the master allows one
of the two signaling bits to be inserted and extracted from the
backplane PCM word to allow simultaneous voice and data
transmission through the PABX. Both UDLTs have a loop-
back feature by which the device can be tested in the user
system.
500 Hz Mu–Law or A–Law coded square wave to the codec–
filter when the TE pin is brought high. This can be used to
provide audio feedback in the telset during keyboard depres-
sions.
GENERAL
mediate data buffers, sequencing and control logic, and
transmit and receive data registers. The data registers
interface to the linecard or codec–filter digital interface sig-
nals, the modulator and demodulator interface the twisted
pair transmission medium, while the intermediate data regis-
ters buffer data between these two sections. The UDLT is
The MC145422 master and MC145426 slave UDLT trans-
The UDLT provides a means for transmitting and receiving
The UDLT operates using one twisted pair. Eight bits of
The slave UDLT has the additional feature of providing a
The UDLT consists of a modulator, demodulator, two inter-
CIRCUIT DESCRIPTION
BACKGROUND
MC145422 MC145426
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