MC145426 Motorola, MC145426 Datasheet - Page 12

• Manufacturer Part Number: MC145426
• Description: (MC145422 / MC145426) UNIVERSAL DIGITAL-LOOP TRANSCEIVER(UDLT)
• Manufacturer: Motorola

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DataSheet
4
intended to operate on a single 5 V supply and can be driven
by TTL or CMOS logic.
MASTER OPERATION
ceive register each frame from the Rx pin under the control of
the TDC/RDC clock and the receive data enable, RE1. RE1
controls loading of eight serial bits, henceforth referred to as
the voice data word. Each MSI, these words are transferred
out of the receive register to the modulation buffer for subse-
quent modulation onto the line. The modulation buffer takes
the receive voice data word and the two signaling data input
bits on SI1 and SI2 loaded on the MSI transition and formats
the 10 bits into a specific order. This data field is then trans-
mitted in a 256 kHz modified DPSK burst onto the line to the
remote slave UDLT.
coded data is transferred to the demodulation buffer and the
signaling bits are stripped ready to be output on SO1 and
SO2 at the next MSI. The voice data word is loaded into the
transmit register as described in the TE1 pin description for
outputting via the Tx pin at the TDC/RDC data clock rate un-
der the control of TE1. VD is output on the rising edge of MSI.
Timing diagrams for the master are shown in Figure 10.
SLAVE OPERATION
incoming line transmission from the master as indicated by
the completion of demodulation. When an incoming burst
from the master is demodulated, several events occur. As in
the master, data is transferred from the demodulator to the
demodulation buffer and the signaling bits are stripped for
outputting at SO1 and SO2. Data in the receive register is
transferred to the modulation buffer. TE1 goes high loading in
data at SI1 and SI2, which will be used in the transmission
burst to the master along with the data in the transmit data
buffer, and outputting SO1, SO2, and VD. Modulation of the
burst begins four 256 kHz periods after the completion of de-
modulation.
codec–filter on the rising edges of the data clock output on
the CLK pin. On the ninth rising edge of CLK, TE1 goes low,
RE1 goes high, and voice data from the codec–filter is input
to the receiver register from the Rx pin on the next eight
falling edges of CLK. RE1 is TE1 inverted and is provided to
facilitate interface to the codec–filter.
MC145422 MC145426
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In the master, data from the linecard is loaded into the re-
Upon demodulating the return burst from the slave, the de-
In the slave, the synchronizing event is the detection of an
While TE1 is high, voice data is output on Tx to the telset
the 4.096 MHz crystal frequency by 32. Slippage between
the frame rate of the master (as represented by the comple-
tion of demodulation of an incoming transmission from the
master) and the crystal frequency is absorbed by holding the
16th low period of CLK until the next completion of demodu-
lation. This is shown in the slave UDLT timing diagram of Fig-
ure 11.
POWER–DOWN OPERATION
and only that circuitry necessary to demodulate the incoming
bursts and output the signaling and VD data bits is active. In
this mode, if the UDLT receives a burst from the slave, the
SO1, SO2, and VD pins will change state upon completion of
the demodulation instead of the the rising edge of MSI. The
state of these pins will not change until either three rising MSI
edges have occurred without the reception of a burst from
the slave or until another burst is demodulated, whichever
occurs first.
three rising MSI edges or until the MSI rising edge following
the demodulation of an incoming burst before transmitting to
the slave. The data for the first transmission to the slave after
power–up is loaded into the UDLT during the RE1 period
prior to the burst in the case of voice, and on the present ris-
ing edge of MSI for signaling data.
drivers such that it can be overdriven externally. When held
low, the UDLT slave is powered–down and only that circuitry
necessary for demodulation, TE1/RE1/CLK generation upon
demodulation, and the outputting of voice and signaling bits
is active. When held high, the UDLT slave is powered–up
and transmits normally in response to transmissions from the
master. If no bursts have been received from the master
within 250 s after power–up (derived from the internal oscil-
lator frequency), the UDLT generates an internal 125 s
free–running clock from the internal oscillator. The slave
UDLT then bursts a transmission to the master UDLT every
other 125 s clock period using data loaded into the Rx pin
during the last RE1 period and SI1, SI2 data loaded in on the
internal 125 s clock edge. The weak output drivers will try to
force PD high when a transmission from the master is demo-
dulated and will try to force it low if 250 s have passed with-
out a transmission from the master. This allows the slave
UDLT to self power–up and down in demand power–loop
systems.
The CLK pin 128 kHz output is formed by dividing down
In the master when PD is low, the UDLT stops modulating
When PD is brought high, the master UDLT will wait either
In the slave, PD is a bidirectional pin with weak output
MOTOROLA