SL1461 Mitel Networks Corporation, SL1461 Datasheet - Page 5

• Manufacturer Part Number: SL1461
• Description: Wideband PLL FM Demodulator
• Manufacturer: Mitel Networks Corporation

DESIGN OF PLL LOOP PARAMETERS
loop and can be represented by the above diagram. For such
a system the following parameters apply;
AFC FACILITY
circuit, which generates DC voltage proportional to the integral
of frequency error. If the incident RF is high then the AFC
voltage increases, if low then the voltage decreases. The AFC
voltage can then be converted by an ADC to be read by the
micro controller for frequency fine tuning; if used in an I
system it is recommended the device is used with either the
SP5055 or SP5056 frequency synthesiser which contains an
internal ADC readable via the I
arbitrary and user defined; if used with the SP5055 it is
suggested the aligned voltage is 0.375 V
the centre code of the ADC on port 6.
around the aligned frequency. The deadband can be adjusted
from zero window to approximately 25MHz width assuming an
oscillator dF/dV of 15MHz/V. If the incident RF is within this
window the AFC voltage does not integrate, except by
component leakage.
demodulated video is fed to a dual comparator where it is
The SL1461SA is normally used as a type 1 second order
The SL1461SA contains an analog frequency error detect
The voltage corresponding to frequency alignment is
The AFC detect circuit contains a deadband centre
With reference to Fig.5; in normal operation the
and
1
2
1
2
K
2
0
n
K
2
n
D
RF INPUT
2
C bus.
CC
GAIN = K
VCO
, corresponding to
D
VOLT/RAD
GAIN = K
R1
2
C
Fig.4
0
RAD SEC/VOLT
compared with two reference voltages, corresponding to the
extremes of the deadband, or window. These voltages are
variable and set by the window adjust input.
corresponding to voltages above or below the voltage window,
or frequency above or below deadband. These digital control
signals are used to control a complimentary current source
pump. The current signals are then fed to the input of an
amplifier which is arranged as an integrator, so integrating the
pulses into a DC voltage.
source and sink are disabled, therefore the DC output voltage
remains constant. There will be a small drift due to component
leakage; the maximum drift can be calculated from;
Note:
From these factors the loop 3dB bandwidth can be determined
from the following expression;
R2
where:
K
K
R1 is loop amplifier input impedance
0
D
n
is the loop damping factor
The comparators produce two digital outputs
If the frequency is correctly aligned both the current
is the VCO gain in radian seconds per volt
is the natural loop bandwidth
is the phase detector gain in volts per radian
K
K
0
D
C1
is dependant on sensitivity of VCO used.
= 0.25V/rad single ended, 0.5V/rad differential
BASEBAND OUTPUT
SL1461SA
5