MT9042 Mitel Networks Corporation, MT9042 Datasheet

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MT9042

Manufacturer Part Number
MT9042
Description
Global Digital Trunk Synchronizer
Manufacturer
Mitel Networks Corporation
Datasheet

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Features
Applications
LOSS1
LOSS2
Provides T1 and E1 clocks, and ST-BUS/GCI
framing signals locked to an input reference of
either 8 kHz (frame pulse), 1.544 MHz (T1), or
2.048 MHz (E1)
Meets AT & T TR62411 and ETSI ETS 300 011
specifications for a 1.544 MHz (T1), or
2.048 MHz (E1) input reference
Provides Time Interval Error (TIE) correction to
suppress input reference rearrangement
transients
Typical unfiltered intrinsic output jitter is
0.013 UI peak-to-peak
Jitter attenuation of 15 dB @ 10 Hz,
34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz
Low power CMOS technology
Synchronization and timing control for T1 and
E1 digital transmission links
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
RSEL
RST
SEC
PRI
VDD
Reference
GTo
Select
MUX
VSS
Automatic State
GTi
Machine
MS1
MS2
Figure 1 - Functional Block Diagram
Corrector
TRST
TIE
FSEL1
Description
The MT9042 is a digital phase-locked loop (PLL)
designed to provide timing and synchronization
signals for T1 and E1 primary rate transmission links
that
alignment timing requirements. The PLL outputs can
be synchronized to either a 2.048 MHz, 1.544 MHz,
or 8 kHz reference. The T1 and E1 outputs are fully
compliant with AT & T TR62411 (ACCUNET
and ETSI ETS 300 011 intrinsic jitter and jitter
transfer
synchronized to primary reference input clock rates
of either 1.544 MHz or 2.048 MHz.
The PLL also provides additional high speed output
clocks at rates of 3.088 MHz, 4.096 MHz, 8.192
MHz, and 16.384 MHz for backplane synchro-
nization.
PLL
Divider
Global Digital Trunk Synchronizer
FSEL2
are
MCLKo
MT9042AP
compatible
specifications,
Ordering Information
Interface
Circuit
-40 C to +85 C
MCLKi
Preliminary Information
28 Pin PLCC
ISSUE 1
with
respectively,
ST-BUS/GCI
MT9042
C3
C1.5
C16
C8
C4
C2
F0o
FP8-STB
FP8-GCI
®
June 1994
frame
when
T1.5)
3-97

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MT9042 Summary of contents

Page 1

... LOSS2 GTo GTi MS1 Global Digital Trunk Synchronizer MT9042AP Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz kHz reference. The T1 and E1 outputs are fully compliant with AT & ...

Page 2

... MT9042 Pin Description Pin # Name 1 V Negative Power Supply Voltage. Nominally 0 Volts TRST TIE Circuit Reset (TTL compatible). When HIGH, the time interval error correction circuit is alternately establishing the phase difference between the PRI and SEC reference inputs, depending upon which input is selected as input for PLL synchronization. This information is used to generate a virtual reference for input to the PLL ...

Page 3

... RST Reset (TTL compatible). This input (active LOW) puts the MT9042 in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the device ...

Page 4

... Detector Filter f ref Divider Figure 3 - PLL Block Diagram As shown in Figure 3, the PLL of the MT9042 consists of a phase detector (PD), a loop filter, a high resolution DCO, and a digital frequency divider. The digitally controlled oscillator (DCO) is locked in frequency ( one of three possible reference ...

Page 5

... GTi 1 C (f) 1 Table 5 - Input Frequency Selection of the MT9042 Time Interval Error Correction Circuit (TIE) The TIE correction circuit generates a virtual input synchronized reference. After a reference rearrangement the TIE corrects the phase of this new reference in such a way that the virtual input preserves its phase. In ...

Page 6

... MT9042 Description State Power On (RST=0 No change LOSS1=X LOSS2=X) LOSS1=0 LOSS2=0 LOSS1=1 LOSS2=0 time loss < tgt LOSS1=1 LOSS2=0 time loss > tgt LOSS1=0 LOSS2=1 LOSS1=1 LOSS2=1 No change Where : ST.GD = Start guard time Don’t care Table 4 - State Table For Automatic Input Reference Selection and Operating Mode ...

Page 7

... AT & T TR62411 and ETSI requirements, respectively. Output Jitter in UIp-p FLT1 10Hz - 8kHz .004 .001 .001 Output Jitter in UIp-p FLT1 20Hz - 100kHz .011 .002 .011 .002 .011 .002 MT9042 of the phase error suppression FLT2 FLT3 10Hz - 40kHz 8kHz - 40kHz .006 .002 .002 .001 .002 .001 . ...

Page 8

... MT9042 Input Jitter Input Jitter Modulation Magnitude Frequency (UIp-p) (Hz 100 20 330 10 500 8 1000 7 5000 0.8 7900 1.044 7950 1.044 7980 1.044 7999 1.044 8001 1.044 8020 1.044 8050 1.044 8100 1.044 10000 0.4 Table 8 - Typical Jitter Transfer Function for the T1 Output ...

Page 9

... MT9042 E1 Reference Input Output Jitter Jitter Magnitude Attenuation (UIp-p) (dB) .351 12.62 .185 18.18 .096 23.88 .039 31.70 .020 37.50 .012 41.94 .007 46.62 .002 54.35 .002 54.35 .002 54.35 .002 54.35 .002 54.35 .002 54.35 .002 54 ...

Page 10

... MT9042 Figure 5 - Typical Jitter Attenuation for T1 Output dB AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA -0 ...

Page 11

... A - Voltages are with respect to ground (V SS ‡ Sym Min Typ Max 2 0 MT9042 Min Max Units -0.3 7.0 V -0 ±150 ±150 ±300 -55 125 900 ) unless otherwise stated. SS Units Test Conditions °C ) unless otherwise stated. ...

Page 12

... MT9042 AC Electrical Characteristics (see Fig. 7) Characteristics 1 8 kHz reference clock period 2 1.544 MHz reference clock period 3 2.048 MHz reference clock period I 4 Input to output propagation delay N with an 8 kHz reference clock P 5 Input to output propagation delay U with a 1.544 MHz reference clock ...

Page 13

... FC4 122 ns P- RC8 FC8 P-C16 RC16 FC16 MT9042 Test Conditions Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Duty cycle on MCLKi =50% 3-109 ...

Page 14

... MT9042 t PD-8 PRI- 8 kHz t PD-20 PRI-2.048 MHz t W-F0o F0o FP8-STB t W-FP8GCI FP8-GCI C16 C1.5 t PD-15 PRI-1.544 MHz 3-110 t W-FP8STB t P-C16 t P- D-20-15 t P-C1.5 Figure 7 - Timing Information for MT9042 Preliminary Information P-C2 t P-C3 ...

Page 15

... Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing t rMCLK 2.4V MCLKi 1.5V 0.4V † - Voltages are with respect to ground (V ‡ Sym Min Typ Max t rMCLKi t fMCLKi t 19.99936 20 20.000640 pMCLKi 40 50 Figure 8 - Master Clock Input MT9042 ) unless otherwise stated. SS Units Test Conditions MHz fMCLK 3-111 ...

Page 16

... MT9042 Notes: 3-112 Preliminary Information ...

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