MT93L16 Mitel Networks Corporation, MT93L16 Datasheet
MT93L16
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MT93L16 Summary of contents
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... Filter Talk Detector -24 -> +21dB User ADV AGC Gain NLP FORMAT ENA1 ENA2 Figure 1 - Functional Block Diagram MT93L16 CMOS Preliminary Information ISSUE3 Ordering Information 36 Pin QSOP - Linear/ /A-Law Program RAM Micro Interface Program ROM Howling Adaptive Controller ...
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... MT93L16 Pin Description Pin # Name 1 ENA1 SSI Enable Strobe / ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe data bits wide, enabling serial PCM data transfer for on Rin/Sout pins ...
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... Preliminary Information Pin Description (continued) Pin # Name 14 RESET Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a low-power stand-by mode. 15 Connect (Output). These pins should be left un-connected. 17 SCLK Serial Port Synchronous Clock (Input). Data clock for the serial microport interface. ...
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... Patent Pending) After echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible. The MT93L16 uses an NLP to remove low level residual echo signals which are not comprised of background noise. The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which disables the NLP during double-talk periods ...
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... This gain is adjustable from -24dB to +21dB in 3dB steps important to use ONLY this user gain function to adjust the speaker volume. The user gain function in the MT93L16 is optimally placed between the two echo cancellers such that no reconvergence is necessary after gain changes. ...
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... The device determines the convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame pulse is applied to the F0i pin, the MT93L16 will assume ST-BUS operation. When a valid GCI (active C4i start of frame (stbus & GCI) ...
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... MT93L16 ...
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... ENA1 ENA2 PCM Law and Format Control (LAW, FORMAT) The PCM companding/coding law used by the MT93L16 is controlled through the LAW and FORMAT pins. ITU-T G.711 companding curves for -Law and A-Law are selected by the LAW pin. PCM coding selected by the FORMAT pin. See Table 4. ...
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... Rout) are clocked out on the rising edge of BCLK. See Figure 13. In ST-BUS and GCI operation, connect the system C4 (4.096MHz) clock to the C4i pin. Master Clock (MCLK) A nominal 20MHz, continuously-running master clock asynchronous with the 8KHz frame. MT93L16 (MCLK) is required. MCLK may be 9 ...
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... X 8bits of memory in their microcontroller system (i.e. external to the MT93L16), from which the MT93L16 can be bootloaded. Registers and program data are loaded into the MT93L16 in the same fashion via the is internally serial microport. Both employ the same command / address / data byte specifi ...
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... A hardware reset (RESET=0) similarly returns the MT93L16 to the ready state for the start of a bootload. Once the program has been loaded, to begin execution from RAM, bootload mode must be ...
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... DATA 1 Transmit SCLK CS This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16. The MT93L16: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high ...
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... MT93L16 Min Max -0.5 5.0 V -0.3 5 -0.3 5 -65 150 90 (typ) ) unless otherwise stated SS Units Test Conditions Test Conditions Measured from Rout -> Sin Measured from Sout -> Rin ) unless otherwise stated. ...
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... MT93L16 AC Electrical Characteristics otherwise stated Characteristics 1 MCLK Frequency 2 BCLK/C4i Clock High 3 BCLK/C4i Clock Low 4 BCLK/C4i Period 5 SSI Enable Strobe to Data Delay (first bit) 6 SSI Data Output Delay (excluding first bit) 7 SSI Output Active to High Impedance 8 SSI Enable Strobe Signal Setup 9 SSI Enable Strobe Signal Hold ...
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... SCH t 250 SCL t 200 CSSI t 100 CSSM t 100 CSH t 100 OHZ Symbol T=1/f CLK Figure 10 - Master Clock - MCLK MT93L16 Max Units Test Notes =150pF =150pF L CMOS Level Units 0.5*V DD 0.9*V DD 0.1*V DD 0.7*V DD 0.3*V ...
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... MT93L16 (O) Sout/Rout t DSD V H (I) C4i F0iS F0iH V H (I) F0i V L start of frame V H (I) Rin/Sin (O) Sout/Rout t DSD V H (I) C4i F0iS F0iH V H (I) F0i V L start of frame V H (I) Rin/Sin V L (O) Sout/Rout (I) BCLK SSS V (I) ENA1 ...
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... I. CMOS input (5V tolerant) (see Table 8 for symbol definitions) DATA INPUT IDS IDH SCH t SCL Figure 14 - INTEL Serial Microport Timing t IDH SCH t SCL Figure 15 - Motorola Serial Microport Timing MT93L16 DATA OUTPUT ODD OHZ SCP CSH SCP ...
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... MT93L16 Register Summary Address: 00h R Power Up LIMIT MUTE_R Reset 00h MSB RESET When high, the power initialization routine is executed presetting all registers to default values. This bit automatically clears itself to’0’ when reset is complete. AH- When high, the Howling detector is disabled and when low the Howling detector is enabled. ...
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... HWLNG - NLPDC NLPC - - Receive Gain Control Register -12dB MT93L16 (ASR not write to this register (LSR not write to this register NBR (RGC ...
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... MT93L16 Address: 16h Read 7 6 Power Up RIPD 7 Reset 00h MSB RIPD 0 RIPD 1 These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte ...
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... ROPD ROPD Send (Sin) Peak Detect Register SIPD SIPD Send (Sin) Peak Detect Register SIPD SIPD SIPD MT93L16 1 (ROPD1 ROPD ROPD ROPD (ROPD2 ROPD ROPD ROPD (SIPD1 SIPD ...
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... MT93L16 Address: 38h Read 7 6 Power Up SEPD SEPD 7 Reset 00h MSB SEPD 0 SEPD 1 These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2 (see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high ...
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... A_AS A_AS A_AS A_AS L_AS L_AS L_AS L_AS L_AS L_AS MT93L16 1 (A_AS1 A_AS A_AS A_AS (A_AS2 A_AS A_AS A_AS (L_AS1 L_AS L_AS L_AS ...
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... MT93L16 Address: 24h R Power Reset 80h MSB - - - RESERVED - - - - L This bit is used in conjunction with Rout Limiter Register 2. (See description below.) 0 Address: 25h R Power Reset 3Eh MSB conjunction with bit 7 (L threshold value in the Rout path Default value is (1f40)h which is equal to 3 ...
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... SIG 2 SIG 1 SIG 0 Firmware Revision Code Register FRC FRC 0 1 Bootload RAM Control Register RAM_ROMb Bootload RAM Signature Register SIG SIG SIG MT93L16 (FRC (BRC BOOT (SIG SIG SIG LSB - LSB SIG 0 LSB 25 ...
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Pin # DETAIL - A Notes: 1. Lead Coplanarity should 0.10mm (.004") max 2. Package surface finishing (2.1) Top Matte: (Charmilles #18-30) (2.2) All Sides: (Charmilles #18-30) (2.3) Bottom Matte: (Charmilles #18-30) ...
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