MT9160 Mitel Networks Corporation, MT9160 Datasheet
MT9160
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MT9160 Summary of contents
Page 1
... Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible micro-controllers. controllerless operation utilizing the default register conditions. The MT9160 is fabricated in Mitel's ISO technology ensuring low power consumption and high reliability. FILTER/CODEC GAIN AAAA AAAA AAAA ...
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... MT9160 20 PIN SOIC 24 PIN PDIP Pin Description Pin # Name SOIC DIP Bias Voltage (Output). (V Bias amplifiers. Connect 0.1 µF capacitor Reference Voltage for Codec (Output). Nominally [(V Ref internally. Connect 0.1 µF capacitor PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low). ...
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... HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced Analog Ground (Input). Nominally 0 volts. SSA Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the handset microphone. 3, Connect. (DIP Package only). 16,21 Description MT9160 7-79 ...
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... Figure 3 depicts the nominal half-channel and side-tone gains for the MT9160. In the event of PWRST, the MT9160 defaults such that the side-tone path is off, all programmable gains are set to 0dB and CCITT -Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI and driver sections are powered up ...
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... Full Scale 0111 1111 0000 0000 Table 1 Transducer Interfaces Standard handset transducer interfaces are provided by the MT9160. These are: • The handset microphone inputs (transmitter), pins M+/M-. The nominal transmit amplifier gain may be adjusted to either 6 15.3 dB. Filter/Codec and Transducer Interface Serial Port ...
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... CS must remain asserted for the duration of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT9160 that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller ...
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... SCLK CS Delays due to internal processor timing which are transparent. The MT9160:-latches received data on the rising edge of SCLK. -outputs transmit data on the falling edge of SCLK. The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data until terminated via CS returning high. ...
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... D- Channel Codec, Digital gain and tone generation) and to provide the channel timing requirements. The MT9160 uses only the first four channels of the 32 channel frame. These channels are always defined, beginning with Channel 0 after the frame pulse, as shown in Figure 7 (ST-BUS assignments). ...
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... V VI VII VIII III Di-bit Group Transmit D-Channel Power-up reset to 1111 1111 Figure 8c - D-Channel 8 kb/s Operation MT9160 Microport Read/Write Access n+2 n+3 n+4* II III Power-up reset to 1111 1111 t =500 nsec max pullup Reset coincident with Read/Write of Address 04 Hex ...
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... Channel 1 conveys the control/status information for the Layer 1 transceiver. C-Channel transferred MSB first on the ST-BUS by the MT9160. The full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheet for the selected transceiver for its C-Channel bit definitions and order of bit transfer. ...
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... Refer to the specifications of Figures 12 & 13 for both synchronous and asynchronous SSI timing. PWRST/Software Reset (Rst) While the MT9160 is held in PWRST no device control or functionality is possible. While in software reset (Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing Rst logic low or by setting the PWRST pin. ...
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... MT9160 Register Summary Gain Control Register 1 RxINC RxFG RxFG Receive Gain RxFG 2 Setting (dB (default RxFG = Receive Filter Gain bit n n RxINC: When high, the receiver driver nominal gain is set to 0 dB. When low, this gain is -6.0 dB. ...
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... Note: Bits marked "-" are reserved bits and should be written with logic "0" ADDRESS = 02h WRITE/READ VERIFY - - - - DrGain ADDRESS = 03h WRITE/READ VERIFY _ TxBsel RxBsel TxMute RxMute MT9160 Power Reset Value XX00 0000 Power Reset Value 0000 0000 7-89 ...
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... D8 When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default). A/µ When high, A-Law encoding/decoding is selected for the MT9160. When low, µ-Law encoding/decoding is selected. Smag/CCITT When high, sign-magnitude code assignment is selected for the Codec input/output. When low, CCITT code assignment is selected for the Codec input/output ...
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... ANALOG ± outputs through the A/D and D/A circuits as well as through the normal transmit A/D MT9160 ADDRESS = 05h WRITE/READ Power Reset Value 1111 1111- write XXXX XXXX - read ADDRESS = 06h WRITE/READ Power Reset Value 1111 1111- write XXXX XXXX - read Power Reset Value ...
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... Twisted Pair 7- Electret Microphone Typical External Gain AV= 5- MT9160 + + Converter Lin MT8972 DNIC Z T Lout 10.24 MHz Figure 9 - Digital Telephone Set Preliminary Information 330 VBias + +5V ...
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... Preliminary Information 1 SLIC Gain Pair MH88622 MT9160 2 SLIC Gain Pair MH88622 7-93 ...
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... MT9160 1 SLIC Gain Pair MH88622 7-94 Preliminary Information 2 SLIC Gain Pair MH88622 ...
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... V V 0.4 ILT SS V 4.5 V IHC 0.5 ILC Sym Min Typ Max Units I 350 DDC1 I 8.0 mA DDFT MT9160 Min Max Units - ± 150 C 750 mW Test Conditions V V Includes Noise margin = 400 mV V Includes Noise margin = 400 ...
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... MT9160 DC Electrical Characteristics Characteristics 1 Input HIGH Voltage TTL inputs 2 Input LOW Voltage TTL inputs 3 Input HIGH Voltage CMOS inputs 4 Input LOW Voltage CMOS inputs 5 VBias Voltage Output 6 V Output Voltage Ref 7 Input Leakage Current 8 Positive Going Threshold Voltage (PWRST only) Negative Going Threshold ...
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... D 360 AX D 750 DX 380 130 750 PSSR 37 PSSR1 40 PSSR2 35 PSSR3 40 MT9160 for µ-Law and 1.477V for rms rms Units Test Conditions Vp-p -Law Vp-p A-Law Both at Codec Transmit filter gain=0dB setting. dB TxINC = 0* dB TxINC = 1* @1020 -40 dBm0 dB -40 to -50 dBm0 ...
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... MT9160 † AC Characteristics for D/A (Receive) Path (V =1.0 volts and V =2.5 volts.) Ref Bias Characteristics 1 Analog output at the Codec full scale 2 Absolute half-channel gain. Din to HSPKR± Tolerance at all other receive filter settings (-1 to -7dB) 3 Gain tracking vs. input level CCITT G.714 Method 2 4 Signal to total distortion vs. input level ...
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... ZL E 300 CL E 0.5 D ‡ Sym Min Typ Max V 2.90 IOLH 1. MT9160 Units Test Conditions dB RxINC = 0* dB RxINC = 1* M± inputs to HSPKR± outputs 1000 Hz at STG2=1 Units Test Conditions ohms across HSPKR± pF each pin: HSPKR+, HSPKR- % 300 ohms load across HSPKR± ...
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... MT9160 AC Electrical Characteristics Characteristics 1 C4i Clock Period 2 C4i Clock High period 3 C4i Clock Low period 4 C4i Clock Transition Time 5 F0i Frame Pulse Setup Time 6 F0i Frame Pulse Hold Time 7 DSTo Delay 8 DSTi Setup Time 9 DSTi Hold Time † Timing is over recommended temperature range & recommended power supply voltages. ...
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... DOHZ DIS t 50 DIH t BCL BCLL t DIH SSS ENW NOTE: Levels refer MT9160 Max Units Test Conditions 1953 ns BCL=4096 kHz to 512 kHz ns BCL=4096 kHz ns BCL=4096 kHz ns Note 1 ns Note 1 - =150 pF, R =1K ...
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... MT9160 AC Electrical Characteristics Characteristics 1 Bit Cell Period 2 Frame Jitter 3 Bit 1 Dout Delay from STB going high 4 Bit 2 Dout Delay from STB going high 5 Bit n Dout Delay from STB going high 6 Bit 1 Data Boundary 7 Din Bit n Data Setup time from STB rising ...
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... CL t 200 CSSI t 100 CSSM t 100 CSH t 100 OHZ DATA INPUT DATA OUTPUT t CYC CYC DATA OUTPUT DATA INPUT Figure 14 - Microport Timing MT9160 Units Test Conditions 150pF 150pF AAAA AAAA ...
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... MT9160 Notes: 7-104 Preliminary Information ...