MT9042C Mitel Networks Corporation, MT9042C Datasheet

no-image

MT9042C

Manufacturer Part Number
MT9042C
Description
Multitrunk System Synchronizer
Manufacturer
Mitel Networks Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT9042CP
Manufacturer:
ZARLINK
Quantity:
262
Part Number:
MT9042CP
Manufacturer:
MITEL
Quantity:
20 000
Part Number:
MT9042CP1
Manufacturer:
ZARLINK
Quantity:
2 100
Part Number:
MT9042CPI
Manufacturer:
HITACHI
Quantity:
5 510
Part Number:
MT9042CPI
Manufacturer:
INF
Quantity:
5 510
Part Number:
MT9042CPR
Manufacturer:
MITEL
Quantity:
785
Features
Applications
Meets jitter requirements for: AT&T TR62411
Stratum 3, 4 and Stratum 4 Enhanced for DS1
interfaces; and for ETSI ETS 300 011, TBR 4,
TBR 12 and TBR 13 for E1 interfaces
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
Provides 8kHz ST-BUS framing signals
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Accepts reference inputs from two independent
sources
Provides bit error free reference switching -
meets phase slope and MTIE requirements
Operates in either Normal, Holdover and
Freerun modes
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
OSCo
RSEL
LOS1
LOS2
OSCi
SEC
PRI
Reference
MS1
Master
Select
Clock
MUX
Reference
Select
Control State Machine
Automatic/Manual
MS2
Corrector
Selected
Refer-
Enable
ence
TIE
RST
Figure 1 - Functional Block Diagram
Corrector
TRST
Circuit
TIE
Select
State
Virtual
Refer-
ence
GTo
Guard Time
Impairment
Description
The MT9042C Multitrunk System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links.
The MT9042C generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9042C is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300
011. It will meet the jitter tolerance, jitter transfer,
intrinsic
accuracy, capture range, phase slope and MTIE
requirements for these specifications.
DS5144
Monitor
Circuit
DPLL
Input
Select
State
GTi
Multitrunk System Synchronizer
MT9042CP
VDD
jitter,
Feedback
VSS
Ordering Information
FS1
-40 C to +85 C
frequency
Frequency
Interface
Output
Circuit
Select
MUX
28 Pin PLCC
ISSUE 2
Advance Information
FS2
accuracy,
MT9042C
September 1999
holdover
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
1

Related parts for MT9042C

MT9042C Summary of contents

Page 1

... The MT9042C generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9042C is compliant with AT&T TR62411 Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic accuracy, capture range, phase slope and MTIE requirements for these specifi ...

Page 2

... MT9042C Pin Description Pin # Name 1,15 V Ground. 0 Volts TRST TIE Circuit Reset (TTL Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a re-alignment of input phase with output phase as shown in Figure 19. The TRST pin should be held low for a minimum of 300ns. ...

Page 3

... See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for dynamic logic threshold values. 5. Unless otherwise stated, all unused inputs should be connected to logic high or logic low and all unused outputs should be left open circuit. Description (see notes The logic level at this input is gated in by the rising MT9042C 3 ...

Page 4

... Control, Mode and Reference Selection of the device. See Tables 1, 4 and 5. Frequency Select MUX Circuit The MT9042C operates with one of three possible input reference frequencies (8kHz, 1.544MHz or 2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference inputs (PRI and SEC) ...

Page 5

... The state diagrams of Figure 7 and 8 indicate under which state changes the TIE Corrector Circuit is activated. Digital Phase Lock Loop (DPLL) As shown in Figure 4, the DPLL of the MT9042C The new virtual consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit. ...

Page 6

... F8o F16o Automatic/Manual Control State Machine The Automatic/Manual Control State Machine allows the MT9042C to be controlled automatically (i.e., LOS1, LOS2 and GTi signals) or controlled manually (i.e., MS1, MS2, GTi and RSEL signals). manual control a single mode of operation (i.e., Normal, Holdover and Freerun) is selected. Under ...

Page 7

... When GTi=0, the state change is to Primary Holdover. When GTi=1, the state change is to Secondary Normal. Master Clock The MT9042C can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. Control and Modes of Operation The MT9042C can operate either in Manual or Automatic Control ...

Page 8

... F8o, F16o) signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz or 2.048MHz. From a reset condition, the MT9042C will take seconds for the output signal to be phase locked to the selected reference. The selection ...

Page 9

... Primary Secondary (000) S1H Holdover Holdover Primary Secondary (010) Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit) Figure 7 - Manual Control State Diagram MT9042C State Normal Holdover Holdover (SEC) (PRI) (SEC) S2 S1H S2H S1 MTIE S1 ...

Page 10

... MT9042C Description Input Controls LOS2 LOS1 GTi RST Legend Change MTIE State change occurs with TIE Corrector Circuit Refer to Automatic Control State Diagram for state changes to and from Auto-Holdover State ...

Page 11

... Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT9042C, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. MT9042C – ...

Page 12

... The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the MT9042C, the output signal phase continuity is maintained to within instance (over one frame) of all reference switches and all mode changes. ...

Page 13

... Manual Control operation and Automatic Control operation. the following Master Clock The MT9042C can use either a clock or crystal as the master timing source. In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the OSCi pin. For applications not ...

Page 14

... MT9042C can be realized by first entering Holdover Mode for a predetermined maximum time (i.e., guard time). If the degraded signal returns to normal before the expiry of the guard time (e.g., 2.5 seconds), then the MT9042C is returned to its Normal Mode (with no reference switch taking place). reference input may be changed from Primary to Secondary. ...

Page 15

... NOTES represents the time delay from when the reference goes D bad to when the MT9042C is provided with a LOS indication. Figure 12 - Automatic Control, Unsymmetrical Guard Time Circuit Timing Example In cases where fast toggling might be expected of the LOS1 input, then an unsymmetrical Guard Time Circuit is recommended. This ensures that reference switching doesn’ ...

Page 16

... STi0 STo1 STi1 F0i C4i Figure 14 - Dual T1 Reference Sources with MT9042C in 1.544MHz Automatic Control When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case holdover was entered for 2s, each mode change sequence could still account for a phase change as large as 350ns. However, there ...

Page 17

... External Stimulus MT8985 STo0 STi0 STo1 STi1 F0i C4i Figure 16 - Dual E1 Reference Sources with MT9042C in 8kHz Manual Control Power Supply Decoupling The MT9042C has two VDD (+5V) pins and two VSS (GND) pins. Power and decoupling capacitors should be included as shown in Figure 17. MT9042C MT9042C ...

Page 18

... MT9042C Absolute Maximum Ratings* - Parameter 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 Storage temperature 5 PLCC package power dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions* - Characteristics 1 Supply voltage 2 Operating temperature ...

Page 19

... Sym Schmitt 0.8 LM Timing Reference Points MT9042C Max Units Conditions/Notes† +0 ppm 5-8 +32 ppm 5-8 +100 ppm 5-8 +0.05 ppm 1,2,4,6-8,40 +0.05 ppm 1,2,4,6-8,40 +0.05 ppm 1,2,4,6-8,40 +230 ppm 1-3,6-8 +198 ppm 1-3,6-8 +130 ...

Page 20

... MT9042C AC Electrical Characteristics - Input/Output Timing Characteristics 1 Reference input pulse width high or low 2 Reference input rise or fall time 3 8kHz reference input to F8o delay 4 1.544MHz reference input to F8o delay 5 2.048MHz reference input to F8o delay 6 F8o to F0o delay 7 F16o setup to C16o falling 8 F16o hold from C16o rising 9 F8o to C1 ...

Page 21

... C8W C8o t C4o C2o C3o C1. R15D R2D F0WL t F16S t C8W t C4W C4W t C2W t t C3W C3W t C15W Figure 20 - Output Timing 1 MT9042C t R8D F8WH F0D F16WL F16H t C16D C8D C4D ...

Page 22

... MT9042C F8o MS1,2 LOS1,2 RSEL, GTi Figure 21 - Input Controls Setup and Hold Timing AC Electrical Characteristics - Intrinsic Jitter Unfiltered Characteristics 1 Intrinsic jitter at F8o (8kHz) 2 Intrinsic jitter at F0o (8kHz) 3 Intrinsic jitter at F16o (8kHz) 4 Intrinsic jitter at C1.5o (1.544MHz) 5 Intrinsic jitter at C2o (2.048MHz) 6 Intrinsic jitter at C3o (3.088MHz) 7 Intrinsic jitter at C4o (4 ...

Page 23

... Sym Min Max Units 1-3,7,9-14,21-22,24,29, 1-3,7,9-14,21-22,24,29, 1-3,7,9-14,21-22,24,29, 1-3,7,9-14,21-22,24,29, 1-3,7,9-14,21-22,24,29, 1-3,7,9-14,21-22,24,29, 1-3,7,9-14,21-22,24,29,35 Sym Min Max Units 2.9 UIpp 1-3,8,9-14,21-22,24,30,35 0.09 UIpp 1-3,8,9-14,21-22,24,30,36 1.3 UIpp 1-3,8,9-14,21-22,24,30,35 0.10 UIpp 1-3,8,9-14,21-22,24,30,36 0.80 UIpp 1-3,8,9-14,21-22,24,30,35 0.10 UIpp 1-3,8,9-14,21-22,24,30,36 0.40 UIpp 1-3,8,9-14,21-22,24,30,35 0.10 UIpp 1-3,8,9-14,21-22,24,30,36 0.06 UIpp 1-3,8,9-14,21-22,24,30,35 0.05 UIpp 1-3,8,9-14,21-22,24,30,36 0.04 UIpp 1-3,8,9-14,21-22,24,30,35 0.03 UIpp 1-3,8,9-14,21-22,24,30,36 0.04 UIpp 1-3,8,9-14,21-22,24,30,35 0.02 UIpp 1-3,8,9-14,21-22,24,30,36 MT9042C Conditions/Notes† Conditions/Notes† Conditions/Notes† 23 ...

Page 24

... MT9042C AC Electrical Characteristics - 8kHz Input Jitter Tolerance Characteristics 1 Jitter tolerance for 1Hz input 2 Jitter tolerance for 5Hz input 3 Jitter tolerance for 20Hz input 4 Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz input 6 Jitter tolerance for 700Hz input 7 Jitter tolerance for 2400Hz input ...

Page 25

... With respect to reference input signal frequency. 38. After a RST or TRST. 39. Master clock duty cycle 40% to 60%. 40. Prior to Holdover Mode, device was in Normal Mode and phase locked. Sym Min Max Units -0 +0 ppm -32 +32 ppm -100 +100 ppm MT9042C Conditions/Notes† 15,18 16,19 17,20 25 ...

Page 26

... MT9042C Dim D (lead coplanarity) A Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) For D & E add for allowable Mold Protrusion 0.010" 20-Pin 28-Pin 44-Pin Min Max Min Max Min 0 ...

Page 27

... Advance Information Notes: MT9042C 27 ...

Page 28

North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors ...

Related keywords