MT8920B Mitel Networks Corporation, MT8920B Datasheet
MT8920B
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MT8920B Summary of contents
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... X 8 Rx0 Dual Port Ram Tx1 Dual Port Ram Address Generator Figure 1 - Functional Block Diagram MT8920B FAMILY ISSUE 6 June 1996 Ordering Information 28 Pin Plastic DIP 28 Pin Ceramic DIP 28 Pin Plastic J-Lead 28 Pin SOIC - Parallel- to-serial STo0 ...
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... MT8920B CMOS 28 1 C4i 2 27 F0i 26 IACK, MS1 3 25 STi0 DS R/ A5, STCH 16 13 VSS PIN PDIP/CERDIP/SOIC Pin Description Pin # Name 1 C4i 4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial bus ...
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... Input 24/32 (pin 25 for 24 channel operation, input 24/32 (pin 25 for 32 channel operation. Description This input is used to select the channel Function (RAMCON for 32 channel operation and D Table 1. STPA Modes of Operation MT8920B CMOS ‡ (RAMCON)= 1 for 24 channel 5 3-5 ...
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... MT8920B CMOS Functional Description The STPA (ST-BUS Parallel Access) device provides a simple interface between Mitel’s ST-BUS and parallel system environments. synchronous, time division, multiplexed bussing scheme with data streams operating at 2048 kbit/s. The ST-BUS is the primary means of access for voice, data and control information to Mitel’s ...
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... Table 2. minimizes this The STPA, in Mode 1, uses signals CS, R/W, DS (Data Strobe), DTACK (Data Acknowledge) IRQ, and IACK (Interrupt Acknowledge) at the parallel interface. of contention is The pinout of the device is shown in Figure 3. MT8920B CMOS When is masked by virtue of Data Strobe (DS) If contention should occur the P access can be completed ...
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... MT8920B CMOS 3-8 ...
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... This bit extends the addressing range for access to Tx1 memory selects “dynamic” interrupt mode selects “dynamic” interrupt mode. 2 Table 3. Control Register 1 Bit Definitions MT8920B CMOS REGISTERS WRITE Tx0 - Channel 0 • • • Tx0 - Channel 31 ...
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... MT8920B CMOS Timing information for data transfers on this interface is shown in Figure 14. The Mode 1 interface is designed to operate directly with a 68000-type asynchronous bus but can easily accommodate most other popular microprocessors as well. Control Registers Two control registers allow control of Mode 1 features. Control Register 1 provides bits to select ...
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... This creates unique vectors which are used by the interrupt service routines. This bypassed by simply not asserting IACK during interrupt acknowledged. In static mode Figure 7 - Interrupt Vector Registers MT8920B CMOS = Tx0 STo0 Rx0 STi0 Tx1 STo1 1 Frame Delay ...
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... MT8920B CMOS Interrupt Modes and Servicing Static Interrupt Mode A static interrupt is caused when an incoming byte matches a predefined byte. The incoming byte from a selected channel is stored in Interrupt Image Register (1/2) where it is compared with the contents of the corresponding Match Byte Register. result of the comparison of individual bits is masked by the contents of the Mask Register (1/2) before it is used to generate an IRQ ...
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... Rx0 - Channel 31 0 Rx0 - Channel 0 • • • • • • 1 Rx0 - Channel 31 Table 6. Mode 2 Address Map MT8920B CMOS This STPA also generates OE (output WE (write enable) to facilitate data When channel N is This signal may be WRITE Tx0 - Channel 0 • • • ...
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... MT8920B CMOS connected directly enable the device appropriately. Common Bus MMS MS1 24/ MMS MS1 24/ Figure 9 - "Daisy-chained" STPA’ Channel Parallel Bus Controller Mode (Mode 3) In order to facilitate efficient use of the parallel bus another signal, similar to STCH, is supplied by the STPA ...
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... MT8920B CMOS 3-15 ...
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... Digital Filtering - Voice Conferencing - Speech/Data Compression - Encryption - Tone Detection and Generation - Frequency Spectrum Analysis - Image Processing - -Law to A-Law Conversion - Echo Cancellation - Modulation - Speech Synthesis and Recognition 74HCT 138 Figure 12 - ST-BUS to DSP Interface MT8920B CS STo0 A5-A0 STi0 D7-D0 STo1 OE WE MMS MS1 24/32 +5V +5V ...
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... The ODE input is used to enable the ST-BUS outputs after all ST-BUS devices are properly configured by software. This contention on the ST-BUS lines during the power-up state. 74HC125 STo0 U1 74HC00 STo1 U2 ODE STo0 STo1 STo7 MT8920B CMOS eliminates the possibility of ST-BUS 3-17 ...
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... MT8920B CMOS Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Supply Voltage 2 Input High Voltage ...
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... ADHT t ARDS t RWDS t RDS t RD DATA OUT t t DHT DST DATA IN Figure 14 - Mode 1 Parallel Bus Timing MT8920B CMOS Max Units Test Conditions Load C CLK ns Load A, C =130pF Load C, C =50pF L ...
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... MT8920B CMOS AC Electrical Characteristics (V =5.0V 5%,T =- Characteristics 1 OE Low to Valid Data 2 Address Access Time 3 CS Low to Valid Data 4 Output Disable 5 Address Setup Time 6 Data Setup Time 7 Data Hold Time 8 Address Hold Time 9 Write Pulse Width 10 OE, R/W High to C4i High 11 OE, R/W Low to C4i Low ...
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... Access begins within contention window but before ST-BUS access. CONDITION 3: OE, R/W t EC4L BUSY CONDITION 4: Access begins during ST-BUS access OE, R/W BUSY Figure 16 - Mode 2 Access Contention Resolution ST-BUS ACCESS (N matches incoming ST-BUS channel) t EC4H t C4BL t C4BH t EBL t EBL MT8920B CMOS CHANNEL ( BIT 7 t C4BH t C4BH 3-21 ...
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... MT8920B CMOS AC Electrical Characteristics ((V =5.0V 5%,TA=- Characteristics OE, WE, Address Enabled 2 C4i Low to Address Change OE, WE, Address Disabled 4 C4i Low to Output Enable Low 5 C4i Low to Output Enable High 6 OE, WE, Pulse Width 7 C4i Low to Write Enable Low 8 C4i Low to Write Enable High ...
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... CHANNEL N-1 BIT 0 BIT 7 C4i STCH t STC Figure 18 - Mode 3 STCH Timing Diagram BIT 4 BIT 3 C4i STCH DCS t STC Figure 19 - Mode 3 DCS Timing Diagram CMOS CHANNEL N BIT 6 BIT 5 t SCPW CHANNEL N BIT 2 BIT 1 BIT 0 t CSPW MT8920B BIT 4 t STC CHANNEL N+1 t STC 3-23 ...
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... MT8920B CMOS AC Electrical Characteristics (V = 5. Characteristics 1 Clock C4i Period 2 Clock C4i Period High 3 Clock C4i Period Low 4 C4i Rise Time 5 C4i Fall Time 6 Frame Pulse Setup Time 7 Frame Pulse Hold Time 8 STo0/1 Delay from C4i 9 STi0 Setup Time ...
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... OUTPUTS 0.8 V Figure 22 - Waveform Test Point Reference C L 6.0k IN4148 LOAD A 125 s CHANNEL 30 (8/2.048) s BIT 6 BIT 5 BIT 4 BIT 3 BIT =150pF L LOAD B Figure 23 - Test Load Circuits MT8920B CMOS CHANNEL CHANNEL 31 0 Bit BIT 1 BIT 0 Data Bus V DD 500 C =130pF L LOAD C 3-25 ...
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... MT8920B CMOS Notes: 3-26 ...