MT93L16 Mitel Networks Corporation, MT93L16 Datasheet - Page 3

• Manufacturer Part Number: MT93L16
• Description: CMOS Low-voltage Acoustic Echo CANceller
• Manufacturer: Mitel Networks Corporation

Preliminary Information
Pin Description (continued)
Notes: 1. All inputs have CMOS compatible, 5V-tolerant logic levels.
Glossary
Double-Talk
Near-end Single-Talk
Far-end Single-Talk
ADV NLP
Howling
Narrowband
NBSD
Noise-Gating
Offset Nulling
Reverberation time
ERL
ERLE
AGC
34,35,36
15, 16
27, 28
Pin #
14
17
18
19
20
21
22
23
24
25
26
29
30
31
32
33
2. All outputs have CMOS logic levels. Rout, Sout, and DATA1 are 5V-tolerant when tristated (to withstand other 5V drivers
on a shared bus).
BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit
RESET
MCLK2
DATA2
DATA1
Name
VDD2
SCLK
VSS2
VDD
Sout
Rout
VSS
NC
CS
NC
F0i
NC
IC
IC
Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a
low-power stand-by mode.
No Connect (Output). These pins should be left un-connected.
Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.
Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low.
Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin
is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and
must be tied to Vss or Vdd.
Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1
pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for
transmitting and receiving data.
No Connect (Output). This pin should be left un-connected.
Positive Power Supply (Input). Nominally 3.3 volts.
Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2’s complement linear PCM format. This is the Send
Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked
out following SSI, ST-BUS, or GCI timing requirements.
Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2’s complement linear PCM format. This is the Receive
out signal after line echo cancellation non-linear processing, AGC, and gain control. Data bits
are clocked out following SSI, ST-BUS, or GCI timing requirements.
Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high)
frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss.
clock. This clock must be synchronous with ENA1, and ENA2 enable strobes.
In ST-BUS or GCI operation, C4i pin must be connected to the 4.096MHz (C4) system clock.
Internal Connection (Input). Tie to Vss.
Digital Ground (Input): Nominally 0 volts.
Positive Power Supply (Input): Nominally 3.3 volts (tie together with VDD, pin 22).
Digital Ground (Input): Nominally 0 volts (tie together with VSS2, pin 29).
No Connect (Output). This pin should be left un-connected.
Master Clock (Input): Nominal 20MHz master clock (tie together with MCLK, pin 8).
Internal Connection (Input). Tie to Vss.
Simultaneous signals present on Rin and Sin.
Signals only present at Sin input.
Signals only present at Rin input.
Advanced Non-Linear-Processor
Oscillation caused by feedback from acoustic and line echo paths
Any mono or dual sinusoidal signals
Narrow Band Signal Detector
Audible switching of background noise
Removal of DC component
The time duration before an echo level decays to -60dBm
Echo Return Loss
Echo Return Loss Enhancement
Automatic Gain Control
Description
MT93L16
3