MACH1 Lattice, MACH1 Datasheet

MACH1

Manufacturer Part Number

MACH1

Description

High-Performance EE CMOS Programmable Logic

Manufacturer

Lattice

Datasheet

1.MACH1.pdf (48 pages)

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FEATURES

Publication# 14051

Amendment/0

High-performance electrically-erasable CMOS PLD families

32 to 128 macrocells

44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

SpeedLocking™ – guaranteed ﬁxed timing up to 16 product terms

Commercial 5/5.5/6/7.5/10/12/15-ns t

Conﬁgurable macrocells

— Programmable polarity

— Registered or combinatorial outputs

— Internal and I/O feedback paths

— D-type or T-type ﬂip-ﬂops

— Output Enables

— Choice of clocks for each ﬂip-ﬂop

— Input registers for MACH 2 family

JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available

Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns

Safe for mixed supply voltage system designs

Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs

Programmable power-down mode results in power savings of up to 75%

Supported by Vantis DesignDirect™ software for rapid logic development

— Supports HDL design methodologies with results optimized for Vantis

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice/Vantis and third-party hardware programming support

— Lattice/VantisPRO™ (formerly known as MACHPRO

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

support on PCs and Automated Test Equipment

and System General

Rev: K

Issue Date: November 1998

MACH 1 and 2 CPLD Families

High-Performance EE CMOS Programmable Logic

and Industrial 7.5/10/12/14/18-ns t

) software for in-system programmability

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