IDT82P20416 Integrated Device Technology, IDT82P20416 Datasheet
IDT82P20416
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IDT82P20416 Summary of contents
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... Short Haul T1/E1/J1 Line Interface Unit IDT82P20416 Version - December 17, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775 Printed in U.S.A. © 2009 Integrated Device Technology, Inc. ...
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... Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
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TABLE OF CONTENTS ........................................................................................................................................................... 3 LIST OF TABLES .................................................................................................................................................................... 6 LIST OF FIGURES ................................................................................................................................................................... 7 FEATURES ............................................................................................................................................................................... 8 APPLICATIONS........................................................................................................................................................................ 9 DESCRIPTION.......................................................................................................................................................................... 9 BLOCK DIAGRAM ................................................................................................................................................................. 10 1 PIN ASSIGNMENT .......................................................................................................................................................... 11 2 PIN DESCRIPTION ......................................................................................................................................................... 12 3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ ...
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... IDT82P20416 3.5.1.1 Bipolar Violation (BPV) / Code Violation (CV) Detection ............................................................. 33 3.5.1.2 Bipolar Violation (BPV) Insertion ................................................................................................. 33 3.5.2 Excessive Zeroes (EXZ) Detection ............................................................................................................. 33 3.5.3 Loss of Signal (LOS) Detection ................................................................................................................... 34 3.5.3.1 Line LOS (LLOS) ......................................................................................................................... 34 3.5.3.2 System LOS (SLOS) ................................................................................................................... 35 3.5.3.3 Transmit LOS (TLOS) ................................................................................................................. 36 3.5.4 Alarm Indication Signal (AIS) Detection and Generation ............................................................................ 37 3.5.4.1 Alarm Indication Signal (AIS) Detection ...................................................................................... 37 3.5.4.2 (Alarm Indication Signal) AIS Generation ................................................................................... 37 3 ...
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... IDT82P20416 6 JTAG ............................................................................................................................................................................... 95 6.1 JTAG INSTRUCTION REGISTER (IR) .................................................................................................................... 95 6.2 JTAG DATA REGISTER .......................................................................................................................................... 95 6.2.1 Device Identification Register (IDR) ............................................................................................................ 95 6.2.2 Bypass Register (BYP) ............................................................................................................................... 95 6.2.3 Boundary Scan Register (BSR) .................................................................................................................. 95 6.3 TEST ACCESS PORT (TAP) CONTROLLER ......................................................................................................... 95 7 THERMAL MANAGEMENT ............................................................................................................................................ 97 7.1 JUNCTION TEMPERATURE ................................................................................................................................... 97 7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................. 97 7.3 HEATSINK EVALUATION ....................................................................................................................................... 97 8 PHYSICAL AND ELECTRICAL SPECIFICATIONS ....................................................................................................... 98 8 ...
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Table-1 Operation Mode Selection ........................................................................................................................................................................... 20 Table-2 Impedance Matching Value in Receive Differential Mode ........................................................................................................................... 21 Table-3 Multiplex Pin Used in Receive System Interface ......................................................................................................................................... 23 Table-4 Multiplex Pin Used in Transmit System Interface ........................................................................................................................................ 25 Table-5 PULS[3:0] Setting in ...
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Figure-1 Functional Block Diagram ............................................................................................................................................................................ 10 Figure-2 484-Pin Fine Pitch BGA (Top View) ............................................................................................................................................................. 11 Figure-3 Switch between Impedance Matching Modes .............................................................................................................................................. 20 Figure-4 Receive Differential Line Interface with Twisted Pair Cable (with transformer) ........................................................................................... 21 Figure-5 Receive Differential Line ...
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... ANSI T1.102, T1.403 and T1.231 • Bellcore TR-TSY-000009, GR-253-CORE and GR-499-CORE • ETSI CTR12/13 • ETS 300166 and ETS 300 233 • G.703, G.735, G.736, G.742, G.772, G.775, G.783 and G.823 • O.161 • ITU I.431 and ITU O.171 8 IDT82P20416 December 17, 2009 DSC-7263/-- ...
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... Remote wireless modules Microwave transmission systems DESCRIPTION The IDT82P20416 is a 16-channel high-density T1/E1/J1 short haul Line Interface Unit. Each channel of the IDT82P20416 can be indepen- dently configured. The configuration is performed through a Serial microprocessor interface. In the receive path, through a Single Ended or Differential line inter- face, the received signal is processed by an adaptive Equalizer and then sent to a Slicer ...
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... IDT82P20416 BLOCK DIAGRAM Block Diagram 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT Figure-1 Functional Block Diagram 10 TDO TDI TCK TMS TRST CLKB CLKA CLKE1 CLKT1 MCKSEL[3:0] MCLK SDO SDI SCLK CS INT RST GPIO[1:0] TEHW TEHWE OE RIM REF VCOM[1:0] VCOMEN December 17, 2009 ...
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... IDT82P20416 1 PIN ASSIGNMENT RD15 TDN14 RDP15 TCLK15 TD14 /TDN15 TDP14 TRING TD15 GNDD C 12 TDP15 TTIP12 TDN15 RDN15 D TRING RCLK1 GNDA GNDA GNDA TTIP13 NC GNDA GNDA VDDD GNDD F TRING RRING ...
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... IDT82P20416 2 PIN DESCRIPTION Name RTIPn Input L3, M3, N3, P3, R3, R20, P20, N20, K20, J20, H20, G20, G3, H3, J3, K3 RRINGn L4, M4, N4, P4, R4, R19, P19, N19, (n=0~15) K19, J19, H19, G19, G4, H4, J4, K4 TTIPn Output M1, P1, T1, V1, Y1, V22, T22, P22, M22, K22, H22, F22, D1, F1, H1, K1 ...
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... IDT82P20416 Name RDn / RDPn Output AA8, Y2, AA2, AA5, AB4, AB20, AA18, AA21, B18, E16, E14, E12, (n=0~15) E11, E9, E7, A5 RDNn Output V9, V5, W7, W8, W9, W19, T15, V18, E17, B16, B14, B12, B11, B9, (n=0~15) RCLKn Output AB7, W4, AA3, AB2, AA7, AA17, AB22, W18, A18, A16, A14, A12, ...
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... IDT82P20416 Name LLOS0 Output TDn / TDPn Input AB5, V4, W6, AA4, AA6, AA16, V19, V17, D18, B17, B15, B13, (n=0~15) B10, B8, B16, C5 TDNn Input / Output AB6, Y3, W5, AB1, AB3, AB19, AB21, AA19, C18, A17, A15, A13, (n=0~15) A10, A8, A6, D5 TCLKn / TDNn Input W10, W3, V6, V7, V8, W17, V16, ...
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... Clock AB18 MCLK: Master Clock Input MCLK provides a stable reference timing for the IDT82P20416. MCLK should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK is informed to the device by MCKSEL[3:0]. If MCLK misses (duty cycle is less than 30% for 10 µs) and then recovers, the device will be reset automatically ...
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... IDT82P20416 Name CLKA Input CLKB Input VCOM[0] Output VCOM[1] VCOMEN Input (Pull-Down) REF - RIM Input (Pull-Down) OE Input TEHWE Input (Pull-Up) TEHW Input (Pull-Up) Pin Description 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT Pin No. AA14 CLKA: External T1/E1 Clock Input A External T1/J1 (1.544 MHz (2.048 MHz) clock is input on this pin. ...
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... IDT82P20416 Name GPIO[0] Output / Input GPIO[1] Input RST Output INT CS Input SCLK Input SDI Input SDO Output Input TRST Pull-Down TMS Input Pull-up TCK Input Pin Description 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT Pin No. V10 GPIO: General Purpose I/O [1:0] These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, GPIO) AA10 respectively ...
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... IDT82P20416 Name TDI Input Pull-up TDO Output VDDIO D8, D13, D15, D17, E10, F12, P13, R10, R11, R16, T7 VDDA N21, M12, N12, M18 VDDD F5, F8, F10, F13, F14, F15, F16, F17, F18, G5, G6, G11, R12, R14, R15, T8, T9, T16, U8, U9 VDDRn ...
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... IDT82P20416 Name A1, A2, A3, A4, A19, A20, A21, A22, B1, B2, B3, B4, B19, B20, B21, B22, C2, C3, C4, C19, C20, C21, C22, D2, D3, D4, D19, D20, D21, D22, E5, E21, F2, F9, F21, G2, G18, G21, H2, H5, H18, H21, J2, J21, K2, K21, L2, L18, L21, M2, N2, N14, P2, P11, P14, P18, P21, ...
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... FUNCTIONAL DESCRIPTION 3 MODE SELECTION The IDT82P20416 can be configured to T1/J1 mode or E1 mode globally per-channel basis. The configuration is determined by the TEHWE pin, the TEHW pin and the T1E1 bit (b0, CHCF,...). Refer to Table-1 for details of the operation mode selection. Table-1 Operation Mode Selection ...
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... IDT82P20416 When RIM is high, impedance matching is configured on a per- channel basis. Three kinds of impedance matching are all supported and selected by the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...). The R_TERM[2] bit (b2, RCF0,...) should be set to match internal or external impedance. If the R_TERM[2] bit (b2, RCF0,...) is ‘ ...
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... IDT82P20416 RTIPn Rr/2 6.0Vpp Rr/2 RRINGn 1. Two Rr/2 resistors should be connected to VCOM[1:0] that are Note: coupled to ground via a 10 µF capacitor, which provide 60 Ω common mode input resistance this mode, lightning protection should be enhanced. 3. The maximum input dynamic range of RTIP/TRING pin is -0.3 V ~3.6 V (in line monitor mode ...
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... IDT82P20416 3.2.3 SLICER The Slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. The input signal is sliced at 50% of the peak value. 3.2.4 R CLOCK & DATA RECOVERY X The Rx Clock & Data Recovery is used to recover the clock signal from the received data accomplished by an integrated Digital Phase Locked Loop (DPLL) ...
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... IDT82P20416 3.2.7 RECEIVER POWER DOWN Set the R_OFF bit (b5, RCF0,...) to ‘1’ will power down the corre- sponding receiver. In this way, the corresponding receive circuit is turned off and the RTIPn/RRINGn pins are forced to High-Z state. The pins on receive system interface (including RDn/RDPn, RDNn, RCLKn) will be in High-Z state if the RHZ bit (b6, RCF0,...) is ‘ ...
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... AMI or HDB3 line code rule. The line code rule is selected by the T_CODE bit (b2, TCF1,...). Functional Description 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT 3.3.4 The IDT82P20416 provides two ways to manipulate the pulse shape before data is transmitted: Interface • Preset Waveform Template; • User-Programmable Arbitrary Waveform. ...
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... Time in Unit Intervals Figure-11 E1 Waveform Template Functional Description 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT PULS[3:0] IDT82P20416 0010 0011 0100 Note: R 0101 0110 Figure-12 E1 Waveform Template Measurement Circuit 0111 Table-6 PULS[3:0] Setting in E1 Mode Interface Conditions E1 75 Ω Internal Impedance matching mode After one of the preset waveform templates is selected, the preset waveform amplitude can be adjusted to get the desired waveform ...
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... IDT82P20416 3.3.4.2 User-Programmable Arbitrary Waveform When the PULS[3:0] bits (b3~0, PULS,...) are set to ‘1XXX’, user- programmable arbitrary waveform will be used in the corresponding channel. Each waveform shape can extend up to divided into 20 sub-phases that are addressed by the SAMP[4:0] bits (b4~0, AWG0,...). The waveform amplitude of each phase is repre- sented by a binary byte, within the range from +63 to -63, stored in the WDAT[6:0] bits (b6~0, AWG1, ...
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... IDT82P20416 Table-7 Transmit Waveform Value for 133 SAMP[4:0] WDAT[6:0] 17H 27H 27H 26H Table-8 Transmit Waveform Value for T1 133 ~ 266 ft SAMP[4: WDAT[6:0] 1BH 2EH 2CH 2AH Table-9 Transmit Waveform Value for T1 266 ~ 399 ft SAMP[4: WDAT[6:0] ...
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... IDT82P20416 3.3.5 LINE DRIVER The Line Driver can be set to High-Z for protection or in redundant applications. The following two ways will set the Line Driver to High-Z: • Setting the OE pin to low will globally set all the Line Drivers to High-Z; • Setting the OE bit (b6, TCF0,...) to ‘0’ will set the corresponding Line Driver to High-Z ...
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... IDT82P20416 TTIPn TRINGn Figure-13 Transmit Differential Line Interface with Twisted Pair Cable (with Transformer) Functional Description 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT 1:2 6.0 Vpp Figure-14 Transmit Differential Line Interface with Co- Figure-15 Transmit Differential Line Interface with Twisted Pair Cable (transformer-less, non standard ...
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... IDT82P20416 3.3.7 TRANSMITTER POWER DOWN Set the T_OFF bit (b5, TCF0,...) to ‘1’ will power down the corre- sponding transmitter. In this way, the corresponding transmit circuit is turned off. The pins on the transmit line interface (including TTIPn and TRINGn) will be in High-Z state. The input on the transmit system interface (including TDn, TDPn, TDNn and TCLK) is ignored ...
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... IDT82P20416 3.4 JITTER ATTENUATOR (RJA & TJA) Two Jitter Attenuators are provided for each channel of receiver and transmitter. Each Jitter Attenuator can be enabled or disabled, as deter- mined by the RJA_EN/TJA_EN bit (b3, RJA/TJA,...) respectively. Each Jitter Attenuator consists of a FIFO and a DPLL, as shown in Figure-16. Jittered Data ...
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... EXZ is monitored in both the receive path and the transmit path. Different line code has different definition of the EXZ. The IDT82P20416 provides two standards of EXZ definition for each kind of line code rule. The standards are ANSI and FCC, as selected by the EXZ_DEF bit (b7, ERR,...). Refer to Table-16 for details. ...
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... IDT82P20416 3.5.3 LOSS OF SIGNAL (LOS) DETECTION The IDT82P20416 detects three kinds of LOS: • LLOS: Line LOS, detected in the receive path; • SLOS: System LOS, detected in the transmit system side; • TLOS: Transmit LOS, detected in the transmit line side. 3.5.3.1 Line LOS (LLOS) The amplitude and density of the data received from the line side are monitored ...
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... IDT82P20416 3.5.3.2 System LOS (SLOS) SLOS can only be detected when the transmit system interface is in Dual Rail NRZ Format mode or in Dual Rail RZ Format mode. The amplitude and density of the data input from the transmit system side are monitored. When the input ‘0’s are equal to or more than N consecutive pulse intervals, SLOS is declared ...
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... IDT82P20416 3.5.3.3 Transmit LOS (TLOS) The amplitude and density of the data output on the transmit line side are monitored. When the amplitude of the data is less than a certain voltage for a certain period, TLOS is declared. The voltage is defined by the TALOS[1:0] bits (b3~2, LOS,...). The period is defined by the TDLOS[1:0] bits (b1~0, LOS, ...
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... IDT82P20416 3.5.4 ALARM INDICATION SIGNAL (AIS) DETECTION AND GEN- ERATION 3.5.4.1 Alarm Indication Signal (AIS) Detection AIS is monitored in both the receive path and the transmit path. When the mark density in the received data or in the data input from the transmit system side meets certain criteria, AIS is declared or cleared ...
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... IDT82P20416 3.5.5 PRBS, QRSS, ARB AND IB PATTERN GENERATION AND DETECTION The pattern includes: Pseudo Random Bit Sequence (PRBS), Quasi- Random Signal Source (QRSS), Arbitrary Pattern (ARB) and Inband Loopback (IB). 3.5.5.1 Pattern Generation The pattern can be generated in the receive path or the transmit path, as selected by the PG_POS bit (b3, PG,...). ...
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... IDT82P20416 3.5.5.2 Pattern Detection Data received from the line side or data input from the transmit system side may be extracted for pattern detection. The direction of data extraction is determined by the PD_POS bit (b3, PD,...). One of PRBS or ARB pattern is selected for detection and IB detection is always active. ...
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... IDT82P20416 Inband Loopback (IB) Detection The IB detection is in compliance with ANSI T1.403. The extracted data is used to compare with the target IB code. The length of the target activate/deactivate IB code can bits, as determined by the IBAL[1:0]/IBDL[1:0] bits (b3~2/b1~0, IBL,...). The content of the target activate/deactivate IB code is programmed in the IBA[7:0]/IBD[7:0] bits (b7~0, IBDA/IBDD, ...
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... IDT82P20416 Automatic Error Counter Updating (CNT_MD = 1) Counting No One second expired? (TMOV_IS = 1 ?) Yes Data in the Error Counter transfers to the ERRCH & ERRCL registers The Error Counter is cleared TMOV_IS is cleared after a '1' is written to it Read the ERRCH & ERRCL registers in the next second ...
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... IDT82P20416 3.5.7 LOOPBACK There are four kinds of loopback: • Analog Loopback • Remote Loopback • Digital Loopback Refer to Figure-1 for loopback location. 3.5.7.1 Analog Loopback Analog Loopback is enabled by the ALP bit (b0, LOOP,...). The data stream to be transmitted on the TTIPn/TRINGn pins is internally looped to the RTIPn/RRINGn pins. ...
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... IDT82P20416 3.5.7.2 Remote Loopback Remote Loopback can be configured manually or automatically. Either manual Remote Loopback configuration or automatic Remote Loopback configuration will enable Remote Loopback. Manual Remote Loopback is enabled by the RLP bit (b1, LOOP,...). Automatic Remote Loopback is enabled when the pattern detection is assigned in the receive path (i.e., the PD_POS bit (b3, PD,...) is ‘0’) and the AUTOLP bit (b3, LOOP,...) is ‘ ...
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... IDT82P20416 3.5.7.3 Digital Loopback The Digital Loopback can be configured manually or automatically. Either manual Digital Loopback configuration or automatic Digital Loop- back configuration will enable Digital Loopback. Manual Digital Loopback is enabled by the DLP bit (b2, LOOP,...). Automatic Digital Loopback is enabled when the pattern detection is assigned in the transmit path (i.e., the PD_POS bit (b3, PD,...) is ‘1’) and the AUTOLP bit (b3, LOOP,...) is ‘ ...
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... IDT82P20416 3.5.8 CHANNEL 0 MONITORING Channel 0 can be used as a monitoring channel when not used as a regular channel. Channel 0 support G.772 Monitoring and Jitter Measurements. 3.5.8.1 G.772 Monitoring Selected by the MON[5:0] bits (b5~0, MON), any receiver or trans- mitter of the other 15 channels can be monitored by channel 0 (as shown in Figure-28). ...
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... IDT82P20416 3.5.8.2 Jitter Measurement (JM) The RJA of channel 0 consists of a Jitter Measurement (JM) module. When the RJA is enabled in channel 0, the JM is used to measure the positive and negative peak value of the demodulated jitter signal of the received data stream. The bandwidth of the measured jitter is selected by the JM_BW bit (b0, JM). ...
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... The IDT82P20416 provides two kinds of clock outputs: • Free running clock outputs on CLKT1 and CLKE1 The following Clock Input is provided: • MCLK as programmable reference timing for the IDT82P20416. 3.6.1 FREE RUNNING CLOCK OUTPUTS ON CLKT1/CLKE1 An internal clock generator uses MCLK as reference to generate all the clocks required by internal circuits and CLKT1/CLKE1 outputs ...
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... IDT82P20416 3.6.2 MCLK, MASTER CLOCK INPUT MCLK provides a stable reference timing for the IDT82P20416. MCLK should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK is set by pins MCKSEL[3:0] and can 1.544 MHz 2.048 MHz with 1 ≤ N ≤ ...
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... IDT82P20416 3.7 INTERRUPT SUMMARY There are altogether 20 kinds of interrupt sources as listed in Table- 23. Among them, No.1 to No.19 are per-channel interrupt sources, while No global interrupt source. For interrupt sources from No.1 to No.10, the occurrence of the event will cause the corresponding Status bit to be set to ‘1’. And selected by the Interrupt Trigger Edges Select bit, either a transition from ‘ ...
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... IDT82P20416 No Functional Description 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT INT active Read TMOV_IS TMOV_IS = 1 ? Yes Serve the interrupt. Read the interrupt status bits Write '1' to clear TMOV_IS. in the corresponding channel. Find the interrupt source and Write '1' to clear the corresponding interrupt status bit. ...
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... MISCELLANEOUS 4.1 RESET The reset operation resets all registers, state machines as well as I/O pins to their default value or status. The IDT82P20416 provides 4 kinds of reset: • Power-on reset; • Hardware reset; • Global software reset; • Per-channel software reset. The Power-on, Hardware and Global software reset operations reset all the common blocks (including clock generator/synthesizer and micro- processor interface) and channel-related parts ...
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... IDT82P20416 4.1.1 POWER-ON RESET Power-on reset is initiated during power-up. When all VDD inputs (1.8V and 3.3V) reach approximately 60% of the standard value of VDD, power-on reset begins. If MCLK is applied, power-on reset will complete within 1 ms maximum; if MCLK is not applied, the device remains in reset state. 4.1.2 HARDWARE RESET Pulling the RST pin to low will initiate hardware reset. The reset cycle should be more than 1 µ ...
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... IDT82P20416 4.3 POWER UP No power up sequencing for the VDD inputs (1.8 V and 3.3 V) has to be provided for the IDT82P20416. A Power-on reset will be initiated during power up. Refer to Section 4.1 Reset. 4.4 HITLESS PROTECTION SWITCHING (HPS) SUM- MARY In today’s telecommunication systems, ensuring no traffic loss is becoming increasingly important. To combat these problems, redun- dancy protection must be built into the systems carrying this traffic ...
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... IDT82P20416 Hot switch control Rx: Fully Internal Impedance Matching mode. In this mode, there is no external resistor required. The R_TERM[2:0] bits (b2~0, RCF0,...) setting is as follows: ‘000’ for T1 100 Ω twisted pair cable, ‘001’ for J1 110 Ω twisted pair cable, ‘010’ for E1 120 Ω twisted pair cable and ‘ ...
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... IDT82P20416 Hot switch control Rx: 75 Ω External Impedance Matching mode. In this mode, there is no external resistor required. The RIM pin should be left open and the configuration of the R_TERM[2:0] bits (b2~0, RCF0,...) is ignored. Tx: 75 Ω Internal Impedance Matching mode. The Figure-35 1+1 HPS Scheme ohm Single-Ended Interface (Shared Common Transformer) ...
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... IDT82P20416 5 PROGRAMMING INFORMATION 5.1 REGISTER MAP 5.1.1 GLOBAL REGISTER Address Register Name (Hex) Common Control 000 ID - Device ID Register 040 RST - Global Reset Register 080 GCF - Global Configuration Register 0C0 MON - G.772 Monitor Configura- tion Register 100 GPIO - General Purpose I/O Pin Definition Register Reference Clock Timing Option 1C0 CLKG - CLKT1 & ...
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... IDT82P20416 5.1.2 PER-CHANNEL REGISTER Only the address of channel 1 is listed in the ‘Address (Hex)’ column of the following table. For the addresses of the other channels, refer to the description of each register. Address Register Name (Hex) Channel Control 001 CHCF - Channel Configuration Register JA Configuration 002 ...
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... IDT82P20416 Address Register Name (Hex) 011 PD - Pattern Detection Control Register 012 ARBL - Arbitrary Pattern Gener- ation / Detection Low-Byte Reg- ister 013 ARBM - Arbitrary Pattern Gen- eration / Detection Middle-Byte Register 014 ARBH - Arbitrary Pattern Gener- ation / Detection High-Byte Reg- ister 015 IBL - Inband Loopback Control ...
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... IDT82P20416 Address Register Name (Hex) Counter 023 ERRCL - Error Counter Low- Byte Register 024 ERRCH - Error Counter High- Byte Register Jitter Measurement (channel 0 Only) 7E5 JM - Jitter Measurement Config- uration For Channel 0 Register 7E6 JIT_PL - Positive Peak Jitter Measurement Low-Byte Regis- ter ...
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... IDT82P20416 5.2 REGISTER DESCRIPTION 5.2.1 GLOBAL REGISTER ID - Device ID Register Address: 000H Type: Read Default Value: 7xH 7 6 ID7 ID6 Bit Name ID[7:0] The ID[7:0] bits are pre-set, where the ID[3:0] bits ‘x’ represent the current version number (‘0000’ is for the first version). RST - Global Reset Register ...
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... IDT82P20416 GCF - Global Configuration Register Address: 080H Type: Read / Write Default Value: 03H Bit Name Reserved. 4 COPY When the per-channel register of one channel is written, this bit determines whether the written value is copied to the same reg- ister of the other channels simultaneously. ...
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... IDT82P20416 GPIO - General Purpose I/O Pin Definition Register Address: 100H Type: Read / Write Default Value: 0FH Bit Name Reserved. 3 LEVEL1 When the GPIO1 pin is defined as output, this bit determines the output level on GPIO1 and can be read and written. 0: Output low level. ...
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... IDT82P20416 CLKG - CLKT1 & CLKE1 Generation Control Register Address: 1C0H Type: Read / Write Default Value: 0FH Bit Name Reserved. 3 CLKE1_EN This bit controls whether the output on the CLKE1 pin is enabled. 0: The output is disabled. CLKE1 is in High-Z state. 1: The output is enabled. The frequency of CLKE1 is determined by the CLKE1 bit (b2, CLKG). (default) ...
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... IDT82P20416 INTCH2 - Interrupt Requisition Source Register 2 Address: 300H Type: Read Default Value: 00H INT_CH15 Bit Name 7 - Reserved INT_CH[15:9] These bits indicate whether there is an interrupt generated in the corresponding channel. The INT_CH[16:9] bits correspond to channel respectively interrupt is generated or all the interrupts are cleared in the corresponding channel. (default least one interrupt is generated in the corresponding channel ...
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... IDT82P20416 5.2.2 PER-CHANNEL REGISTER CHCF - Channel Configuration Register Address: 001H, 041H, 081H, 0C1H, 101H, 141H, 181H, 1C1H, (CH1~CH8) 201H, 241H, 281H, 2C1H, 301H, 341H, 381H, (CH9~CH15) 7C1H (CH0) Type: Read / Write Default Value: 00H Bit Name Reserved. 1 CHRST Writing a ‘1’ to this bit will initiate per-channel software reset. Once initiated, per-channel software reset completes in 1 µs maxi- mum ...
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... IDT82P20416 RJA - Receive Jitter Attenuation Configuration Register Address: 003H, 043H, 083H, 0C3H, 103H, 143H, 183H, 1C3H, (CH1~CH8) 203H, 243H, 283H, 2C3H, 303H, 343H, 383H, (CH9~CH15) 7C3H (CH0) Type: Read / Write Default Value: 00H Bit Name Reserved. 4 RJA_LIMT This bit determines whether the JA-Limit function is enabled in the RJA. ...
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... IDT82P20416 TCF0 - Transmit Configuration Register 0 Address: 004H, 044H, 084H, 0C4H, 104H, 144H, 184H, 1C4H, (CH1~CH8) 204H, 244H, 284H, 2C4H, 304H, 344H, 384H, (CH9~CH15) 7C4H (CH0) Type: Read / Write Default Value: 00H Bit Name 7 - Reserved This bit determines the output of the Line Driver, i.e., the output on the TTIPn and TRINGn pins. ...
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... IDT82P20416 TCF1 - Transmit Configuration Register 1 Address: 005H, 045H, 085H, 0C5H, 105H, 145H, 185H, 1C5H, (CH1~CH8) 205H, 245H, 285H, 2C5H, 305H, 345H, 385H, (CH9~CH15) 7C5H (CH0) Type: Read / Write Default Value: 01H Bit Name Reserved. 4 TCK_ES This bit selects the active edge of the TCLKn pin. ...
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... IDT82P20416 PULS - Transmit Pulse Configuration Register Address: 006H, 046H, 086H, 0C6H, 106H, 146H, 186H, 1C6H, (CH1~CH8) 206H, 246H, 286H, 2C6H, 306H, 346H, 386H, (CH9~CH15) 7C6H (CH0) Type: Read / Write Default Value: 02H Bit Name Reserved PULS[3:0] These bits select one of the eight preset waveform templates for short haul application or enable user-programmable arbitrary waveform ...
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... IDT82P20416 SCAL - Amplitude Scaling Control Register Address: 007H, 047H, 087H, 0C7H, 107H, 147H, 187H, 1C7H, (CH1~CH8) 207H, 247H, 287H, 2C7H, 307H, 347H, 387H, (CH9~CH15) 7C7H (CH0) Type: Read / Write Default Value: 36H Bit Name Reserved SCAL[5:0] These bits specify a scaling factor to be applied to the amplitude of the waveform to be transmitted. ...
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... IDT82P20416 AWG1 - Arbitrary Waveform Generation Control Register 1 Address: 009H, 049H, 089H, 0C9H, 109H, 149H, 189H, 1C9H, (CH1~CH8) 209H, 249H, 289H, 2C9H, 309H, 349H, 389H, (CH9~CH15) 7C9H (CH0) Type: Read / Write Default Value: 00H WDAT6 Bit Name 7 - Reserved WDAT[6:0] These bits are valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...) are set to ‘ ...
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... IDT82P20416 RCF0 - Receive Configuration Register 0 Address: 00AH, 04AH, 08AH, 0CAH, 10AH, 14AH, 18AH, 1CAH, (CH1~CH8) 20AH, 24AH, 28AH, 2CAH, 30AH, 34AH, 38AH, (CH9~CH15) 7CAH (CH0) Type: Read / Write Default Value: 47H 7 6 RCKH RHZ Bit Name 7 RCKH This bit determines the output on RCLKn when LLOS is detected. This bit is valid only when LLOS is detected and the AIS and pattern generation is disabled in the receive path ...
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... IDT82P20416 RCF1 - Receive Configuration Register 1 Address: 00BH, 04BH, 08BH, 0CBH, 10BH, 14BH, 18BH, 1CBH, (CH1~CH8) 20BH, 24BH, 28BH, 2CBH, 30BH, 34BH, 38BH, (CH9~CH15) 7CBH (CH0) Type: Read / Write Default Value: 01H Bit Name Reserved. 4 RCK_ES This bit selects the active edge of the RCLKn pin. ...
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... IDT82P20416 LOS - LOS Configuration Register Address: 00DH, 04DH, 08DH, 0CDH, 10DH, 14DH, 18DH, 1CDH, (CH1~CH8) 20DH, 24DH, 28DH, 2CDH, 30DH, 34DH, 38DH, (CH9~CH15) 7CDH (CH0) Type: Read / Write Default Value: 15H 7 6 LAC ALOS2 Bit Name 7 LAC This bit selects the LLOS, SLOS and AIS criteria. ...
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... IDT82P20416 TDLOS[1:0] These bits select the period. When the amplitude of the data is less than a certain voltage for the period, TLOS is declared. The voltage is determined by the TALOS bits (b3~2, LOS,...). 00: 16-pulse. 01: 32-pulse. (default) 1X: 64-pulse. ERR - Error Detection & Insertion Control Register Address: 00EH, 04EH, 08EH, 0CEH, 10EH, 14EH, 18EH, 1CEH, (CH1~CH8) ...
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... IDT82P20416 AISG - AIS Generation Control Register Address: 00FH, 04FH, 08FH, 0CFH, 10FH, 14FH, 18FH, 1CFH, (CH1~CH8) 20FH, 24FH, 28FH, 2CFH, 30FH, 34FH, 38FH, (CH9~CH15) 7CFH (CH0) Type: Read / Write Default Value: 00H Bit Name Reserved. 4 TXAIS This bit controls the transmission of AIS in the transmit path. ...
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... IDT82P20416 PG - Pattern Generation Control Register Address: 010H, 050H, 090H, 0D0H, 110H, 150H, 190H, 1D0H, (CH1~CH8) 210H, 250H, 290H, 2D0H, 310H, 350H, 390H, (CH9~CH15) 7D0H (CH0) Type: Read / Write Default Value: 00H PG_CK Bit Name 7 - Reserved. 6 PG_CK This bit selects the reference clock when the pattern (including PRBS, ARB & IB) is generated. ...
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... IDT82P20416 PD - Pattern Detection Control Register Address: 011H, 051H, 091H, 0D1H, 111H, 151H, 191H, 1D1H, (CH1~CH8) 211H, 251H, 291H, 2D1H, 311H, 351H, 391H, (CH9~CH15) 7D1H (CH0) Type: Read / Write Default Value: 03H Bit Name Reserved. 3 PD_POS This bit selects the pattern (including PRBS, ARB & IB) detection direction. ...
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... IDT82P20416 ARBL - Arbitrary Pattern Generation / Detection Low-Byte Register Address: 012H, 052H, 092H, 0D2H, 112H, 152H, 192H, 1D2H, (CH1~CH8) 212H, 252H, 292H, 2D2H, 312H, 352H, 392H, (CH9~CH15) 7D2H (CH0) Type: Read / Write Default Value: 55H 7 6 ARB7 ARB6 Bit Name ARB[7:0] These bits, together with the ARB[23:8] bits, define the ARB pattern to be generated or detected ...
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... IDT82P20416 IBL - Inband Loopback Control Register Address: 015H, 055H, 095H, 0D5H, 115H, 155H, 195H, 1D5H, (CH1~CH8) 215H, 255H, 295H, 2D5H, 315H, 355H, 395H, (CH9~CH15) 7D5H (CH0) Type: Read / Write Default Value: 01H Bit Name Reserved IBGL[1:0] These bits define the length of the valid IB generation code programmed in the IBG[7:0] bits (b7~0, IBG,...). ...
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... IDT82P20416 IBDA - Inband Loopback Detection Target Activate Code Definition Register Address: 017H, 057H, 097H, 0D7H, 117H, 157H, 197H, 1D7H, (CH1~CH8) 217H, 257H, 297H, 2D7H, 317H, 357H, 397H, (CH9~CH15) 7D7H (CH0) Type: Read / Write Default Value: 01H 7 6 IBA7 IBA6 Bit Name ...
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... IDT82P20416 LOOP - Loopback Control Register Address: 019H, 059H, 099H, 0D9H, 119H, 159H, 199H, 1D9H, (CH1~CH8) 219H, 259H, 299H, 2D9H, 319H, 359H, 399H, (CH9~CH15) 7D9H (CH0) Type: Read / Write Default Value: 00H Bit Name Reserved. 3 AUTOLP This bit determines whether automatic Digital/Remote Loopback is enabled. ...
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... IDT82P20416 INTES - Interrupt Trigger Edges Select Register Address: 01AH, 05AH, 09AH, 0DAH, 11AH, 15AH, 19AH, 1DAH, (CH1~CH8) 21AH, 25AH, 29AH, 2DAH, 31AH, 35AH, 39AH, (CH9~CH15) 7DAH (CH0) Type: Read / Write Default Value: 00H AIS_IES Bit Name 7 - Reserved. 6 AIS_IES This bit selects the transition edge of the LAIS_S bit (b6, STAT1,...) and the SAIS_S bit (b7, STAT1,...). ...
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... IDT82P20416 INTM0 - Interrupt Mask Register 0 Address: 01BH, 05BH, 09BH, 0DBH, 11BH, 15BH, 19BH, 1DBH, (CH1~CH8) 21BH, 25BH, 29BH, 2DBH, 31BH, 35BH, 39BH, (CH9~CH15) 7DBH (CH0) Type: Read / Write Default Value: FFH 7 6 DAC_IM TJA_IM Bit Name 7 DAC_IM This bit is the waveform amplitude overflow interrupt mask. ...
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... IDT82P20416 INTM1 - Interrupt Mask Register 1 Address: 01CH, 05CH, 09CH, 0DCH, 11CH, 15CH, 19CH, 1DCH, (CH1~CH8) 21CH, 25CH, 29CH, 2DCH, 31CH, 35CH, 39CH, (CH9~CH15) 7DCH (CH0) Type: Read / Write Default Value: EFH 7 6 SAIS_IM LAIS_IM Bit Name 7 SAIS_IM This bit is the SAIS interrupt mask. ...
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... IDT82P20416 INTM2 - Interrupt Mask Register 2 Address: 01DH, 05DH, 09DH, 0DDH, 11DH, 15DH, 19DH, 1DDH, (CH1~CH8) 21DH, 25DH, 29DH, 2DDH, 31DH, 35DH, 39DH, (CH9~CH15) 7DDH (CH0) Type: Read / Write Default Value: 3FH Bit Name Reserved. 5 SBPV_IM This bit is the SBPV interrupt mask. ...
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... IDT82P20416 STAT0 - Status Register 0 Address: 01EH, 05EH, 09EH, 0DEH, 11EH, 15EH, 19EH, 1DEH, (CH1~CH8) 21EH, 25EH, 29EH, 2DEH, 31EH, 35EH, 39EH, (CH9~CH15) 7DEH (CH0) Type: Read Default Value: 00H 7 6 AUTOLP_S - Bit Name 7 AUTOLP_S This bit indicates the automatic Digital/Remote Loopback status. ...
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... IDT82P20416 STAT1 - Status Register 1 Address: 01FH, 05FH, 09FH, 0DFH, 11FH, 15FH, 19FH, 1DFH, (CH1~CH8) 21FH, 25FH, 29FH, 2DFH, 31FH, 35FH, 39FH, (CH9~CH15) 7DFH (CH0) Type: Read Default Value: 00H 7 6 SAIS_S LAIS_S Bit Name 7 SAIS_S This bit indicates the SAIS status. ...
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... IDT82P20416 INTS0 - Interrupt Status Register 0 Address: 020H, 060H, 0A0H, 0E0H, 120H, 160H, 1A0H, 1E0H, (CH1~CH8) 220H, 260H, 2A0H, 2E0H, 320H, 360H, 3A0H, (CH9~CH15) 7E0H (CH0) Type: Read / Write Default Value: 00H 7 6 DAC_IS TJA_IS Bit Name 7 DAC_IS This bit indicates the interrupt status of the waveform amplitude overflow. ...
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... IDT82P20416 INTS1 - Interrupt Status Register 1 Address: 021H, 061H, 0A1H, 0E1H, 121H, 161H, 1A1H, 1E1H, (CH1~CH8) 221H, 261H, 2A1H, 2E1H, 321H, 361H, 3A1H, (CH9~CH15) 7E1H (CH0) Type: Read / Write Default Value: 00H 7 6 SAIS_IS LAIS_IS Bit Name 7 SAIS_IS This bit indicates the interrupt status of the SAIS. ...
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... IDT82P20416 INTS2 - Interrupt Status Register 2 Address: 022H, 062H, 0A2H, 0E2H, 122H, 162H, 1A2H, 1E2H, (CH1~CH8) 222H, 262H, 2A2H, 2E2H, 322H, 362H, 3A2H, (CH9~CH15) 7E2H (CH0) Type: Read / Write Default Value: 00H Bit Name Reserved. 5 SBPV_IS This bit indicates the interrupt status of the SBPV. ...
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... IDT82P20416 ERRCL - Error Counter Low-Byte Register Address: 023H, 063H, 0A3H, 0E3H, 123H, 163H, 1A3H, 1E3H, (CH1~CH8) 223H, 263H, 2A3H, 2E3H, 323H, 363H, 3A3H, (CH9~CH15) 7E3H (CH0) Type: Read Default Value: 00H 7 6 ERRC7 ERRC6 Bit Name ERRC[7:0] These bits, together with the ERRC[15:8] bits, reflect the accumulated error number in the internal Error Counter. They are updated automatically or manually, as determined by the CNT_MD bit (b1, ERR,...). They should be read in the next round of error counting ...
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... IDT82P20416 JM - Jitter Measurement Configuration For Channel 0 Register Address: 7E5H Type: Read / Write Default Value: 00H Bit Name Reserved. 2 JM_STOP This bit is valid only when the JM_MD bit (b1, JM) is ‘0’. A transition from ‘0’ to ‘1’ on this bit updates the JIT_PH, JIT_PL and JIT_NH, JIT_NL registers. ...
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... IDT82P20416 JIT_NL - Negative Peak Jitter Measurement Low-Byte Register Address: 7E8H Type: Read Default Value: 00H 7 6 JIT_N7 JIT_N6 Bit Name JIT_N[7:0] These bits, together with the JIT_N[11:8] bits, reflect the greatest negative peak value of the demodulated jitter signal which is measured by channel 0. They are updated automatically or manually, as determined by the JM_MD bit (b1, JM). They should be read in the next round of jitter measurement ...
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... IDT82P20416 6 JTAG The IDT82P20416 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) controller. The control of the TAP is achieved through signals applied to the Test Mode Select (TMS) and Test Clock (TCK) input pins ...
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... IDT82P20416 1 Test-logic Reset 0 0 Run Test/Idle JTAG 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT 1 1 Select- Capture- Shift- Exit1- Pause- Exit2-DR 1 Update- Figure-37 JTAG State Diagram 96 1 Select- Capture- Shift- Exit1- Pause-IR ...
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... Junction-to-Ambient Thermal Resistance of the package Junction Temperature Ambient Temperature Device Power Consumption For the IDT82P20416, the above values are: θ = 23.7 °C/W (when airflow rate is 0 m/s. See the above table ) 125 °C jmax ° ° Refer to Section 8 ...
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... IDT82P20416 8 PHYSICAL AND ELECTRICAL SPECIFICATIONS 8.1 ABSOLUTE MAXIMUM RATINGS Symbol VDDD Digital Core Power Supply VDDA Analog Core Power Supply VDDIO I/O Power Supply VDDT0~15 Power Supply for Transmitter Driver VDDR0~15 Power Supply for Receiver Input Voltage, Any Digital Pin V Input Voltage, Any RTIP and RRING pin ...
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... IDT82P20416 8.2 RECOMMENDED OPERATING CONDITIONS Symbol T Operating Temperature Range op VDDIO Digital I/O Power Supply VDDA Analog Core Power Supply VDDD Digital Core Power Supply VDDT Power Supply for Transmitter Driver VDDR Power Supply for Receiver V Input Low Voltage IL V Input High Voltage IH Note: 1 ...
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... IDT82P20416 8.3 DEVICE POWER CONSUMPTION AND DISSIPATION (TYPICAL) Total Consumption (W) Mode Parameter 1.8 V E1/120 Ω PRBS 0.18 100% ones 0.18 E1/75 Ω PRBS 0.18 100% ones 0.18 T1/100 Ω QRSS 0.14 100% ones 0.14 J1/110 Ω QRSS 0.14 100% ones 0.14 Note: 1. Test conditions: VDDx (typical °C operating temperature (ambient). 2. The R_OFF bit (b5, RCF0,...) and T_OFF bit (b5, TCF0,...) are set to ‘1’ to enable per-channel power down. ...
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... IDT82P20416 8.4 DEVICE POWER CONSUMPTION AND DISSIPATION (MAXIMUM) Mode Parameter E1/120 Ω PRBS 100% ones E1/75 Ω PRBS 100% ones T1/100 Ω QRSS 100% ones J1/110 Ω QRSS 100% ones Note: 1. Test conditions: VDDx (maximum °C operating temperature (ambient). 2. The transmitter is in Internal Impedance Matching mode and the receiver is in Fully Internal Impedance Matching mode. That is, the R120IN bit (b4, RCF0,...) is set to ‘1’. And the T_TERM[2:0] bits (b2~0, TCF0,...) and R_TERM[2:0] bits (b2~0, RCF0,...) are set according to different cable conditions. 3. The transmitter is in Internal Impedance Matching mode and the receiver is in Partially Internal Impedance Matching mode. That is, the R120IN bit (b4, RCF0,...) is set to ‘ ...
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... IDT82P20416 8.5 D.C. CHARACTERISTICS @ TA = -40 to +85 °C, VDDIO = 3.3 V ± 5%, VDDD = 1.8 V ± 5% Symbol Parameter V Output Low Voltage OL V Output High Voltage OH V Schmitt Trigger Input Low to High Threshold T+ V Schmitt Trigger Input High to Low Threshold T- R Internal Pull-up /Pull-down Resistor pu I Input Low Current ...
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... IDT82P20416 8.6 E1 RECEIVER ELECTRICAL CHARACTERISTICS Parameter Receiver Sensitivity of Receive Differen- tial mode with Cable Loss @ 1024 KHz Receiver Sensitivity of Receive Single Ended mode with Cable Loss @ 1024 kHz Signal to Noise Interference Margin Analog LOS Level ALOS[2:0] (Normal Mode) 000 001 (default) 010 ...
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... IDT82P20416 Parameter Receiver Single Ended mode Input Impedance to GND Receive Return Loss: 51 KHz ~ 102 KHz 102 KHz ~ 2.048 MHz 2.048 MHz ~ 3.072 MHz Receive Path Delay: Single Rail Dual Rail NRZ Dual Rail RZ Physical And Electrical Specifications 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT Min Typ ...
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... IDT82P20416 8.7 T1/J1 RECEIVER ELECTRICAL CHARACTERISTICS Parameter Receiver Sensitivity of Receive Differen- tial mode with Cable Loss @ 772 KHz Receiver Sensitivity of Receive Single Ended mode with Cable Loss @ 772 KHz Signal to Noise Interference Margin Analog LOS Level ALOS[2:0] (Normal Mode) 000 001 (default) 010 ...
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... IDT82P20416 8.8 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS Parameter Output Pulse Amplitude: E1, 75 Ω load E1, 120 Ω load Zero (Space) Level: E1, 75 Ω load E1, 120 Ω load Transmit Amplitude Variation with Supply Difference between Pulse Sequences for 17 consecutive pulses (T1.102) Output Pulse Width at 50% of Nominal Amplitude Ratio of the Amplitudes of Positive and Negative Pulses at the Center of the Pulse Interval (G ...
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... IDT82P20416 8.9 T1/J1 TRANSMITTER ELECTRICAL CHARACTERISTICS Parameter Output Pulse Amplitude Zero (Space) Level Transmit Amplitude Variation with Supply Difference between Pulse Sequences for 17 consecutive pulses (T1.102) Output Pulse Width at 50% of Nominal Amplitude Pulse Width Variation at the Half Amplitude (T1.102) Imbalance between Positive and Negative Pulses Amplitude (T1 ...
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... IDT82P20416 8.10 TRANSMITTER AND RECEIVER TIMING CHARACTERISTICS Symbol MCLK Frequency: E1 T1/J1 MCLK Tolerance MCLK Duty Cycle Transmit Path TCLK Frequency: E1 T1/J1 TCLK Tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay Time of OE low to Driver High-Z Receive Path Clock Recovery Capture Range ...
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... IDT82P20416 TCLKn TDn/TDPn TDNn RCLK RDn/RDPn (RCK_ES = 0) RDNn RDn/RDPn (RCK_ES = 1) RDNn Physical And Electrical Specifications 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT t1 Figure-38 Transmit Clock Timing Diagram Figure-39 Receive Clock Timing Diagram 109 t2 t8 December 17, 2009 ...
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... IDT82P20416 8.11 CLKE1 TIMING CHARACTERISTICS Symbol CLKE1 outputs 2.048 MHz clock t1 CLKE1 Pulse Width t2 CLKE1 Pulse Width High Time t3 CLKE1 Pulse Width Low Time t4 LLOS Data Setup Time t5 LLOS Data Hold Time CLKE1 outputs 8kHz clock t1 CLKE1 Pulse Width t2 CLKE1 Pulse Width High Time ...
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... IDT82P20416 8.12 JITTER ATTENUATION CHARACTERISTICS Parameter Jitter Transfer Function Corner (-3 dB) Frequency: E1, 32/64/128-bit FIFO T1/J1, 32/64/128-bit FIFO Jitter Attenuator: E1 (G.736) T1/J1 (AT&T pub.62411) Jitter Attenuator Latency Delay: 32-bit FIFO 64-bit FIFO 128-bit FIFO Input Jitter Tolerance before FIFO Overflow or Underflow: 32-bit FIFO 64-bit FIFO ...
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... IDT82P20416 Physical And Electrical Specifications 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT Figure-41 E1 Jitter Tolerance Performance Figure-42 T1/J1 Jitter Tolerance Performance 112 December 17, 2009 ...
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... IDT82P20416 Physical And Electrical Specifications 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT Figure-43 E1 Jitter Transfer Performance Figure-44 T1/J1 Jitter Transfer Performance 113 December 17, 2009 ...
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... IDT82P20416 8.13 MICROPROCESSOR INTERFACE TIMING 8.13.1 SERIAL MICROPROCESSOR INTERFACE A falling transition on CS indicates the start of a read/write operation, and a rising transition indicates the end of the operation. After CS is set to low, a 5-bit instruction on SDI is input to the device on the rising edge of SCLK. If the MSB is ‘1’ read operation. If the MSB is ‘0’ ...
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... IDT82P20416 Symbol f SCLK Frequency OP t Minimum CS High Time CSH t CS Setup Time CSS t CS Hold Time CSD t Clock Disable Time CLD t Clock High Time CLH t Clock Low Time CLL t Data Setup Time DIS t Data Hold Time DIH t Output Delay PD t Output Disable Time ...
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... IDT82P20416 8.14 JTAG TIMING CHARACTERISTICS Symbol Parameter t1 TCK Period t2 TMS to TCK Setup Time; TDI to TCK Setup Time t3 TCK to TMS Hold Time; TCK to TDI Hold Time t4 TCK to TDO Delay Time TCK TMS TDI TDO Physical And Electrical Specifications 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT ...
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AIS — AMI — ARB — B8ZS — BPV — CF — CV — DPLL — EXZ — FIFO — HDB3 — HPS — IB — LAIS — LBPV — LEXZ — LLOS — LOS — NRZ — PBX — ...
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... IDT82P20416 SEXZ — SLOS — SONET — TEPBGA — TJA — TLOS — TOC — Glossary 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT System Excessive Zeroes System LOS Synchronous Optical Network Thermally Enhanced Plastic Ball Grid Array Transmit Jitter Attenuator Transmit Loss of Signal ...
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A Alarm Indication Signal (AIS) ............................................................. 37 B Bipolar Violation (BPV) ....................................................................... 33 C cable coaxial cable ........................................................................ 20 twisted pair cable ................................................................. 20 clock input MCLK ......................................................................................... 48 XCLK .......................................................................................... 48 clock output CLKT1/CLKE1 ............................................................................ 47 Code Violation (CV) ...
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... IDT82P20416 power down ................................................................................. 24 receiver ....................................................................................... 24 transmitter ................................................................................... 31 Protected Non-Intrusive Monitoring .................................................... 22 R receive sensitivity ............................................................................... 22 reset global software reset .................................................................. 52 hardware reset ............................................................................ 52 power-on reset ............................................................................ 52 Rx clock & data recovery .................................................................... 23 S slicer ................................................................................................... 23 Index 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT , 31 system interface .................................................................... 13 receive Dual Rail NRZ Format .............................................................. 23 Dual Rail RZ Format ...
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... IDT82P20416 IDT82P20416 ORDERING INFORMATION XXXXXXX XX Device Type Package CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT X Process/Temperature Range BLANK BF BFG 82P20416 82P20416D ...