IDT82P20416 Integrated Device Technology, IDT82P20416 Datasheet - Page 7

• Manufacturer Part Number: IDT82P20416
• Description: 16-channel Short Haul T1/e1/j1 Line Interface Unit
• Manufacturer: Integrated Device Technology

List of Figures
Figure-1 Functional Block Diagram ............................................................................................................................................................................ 10
Figure-2 484-Pin Fine Pitch BGA (Top View) ............................................................................................................................................................. 11
Figure-3 Switch between Impedance Matching Modes .............................................................................................................................................. 20
Figure-4 Receive Differential Line Interface with Twisted Pair Cable (with transformer) ........................................................................................... 21
Figure-5 Receive Differential Line Interface with Coaxial Cable (with transformer) ................................................................................................... 21
Figure-6 Receive Differential Line Interface with Twisted Pair Cable (transformer-less, non standard compliant) .................................................... 22
Figure-7 Receive Path Monitoring .............................................................................................................................................................................. 22
Figure-8 Transmit Path Monitoring ............................................................................................................................................................................. 22
Figure-9 DSX-1 Waveform Template ......................................................................................................................................................................... 25
Figure-10 T1 Waveform Template Measurement Circuit ............................................................................................................................................. 25
Figure-11 E1 Waveform Template ............................................................................................................................................................................... 26
Figure-12 E1 Waveform Template Measurement Circuit ............................................................................................................................................ 26
Figure-13 Transmit Differential Line Interface with Twisted Pair Cable (with Transformer) ........................................................................................ 30
Figure-14 Transmit Differential Line Interface with Coaxial Cable (with transformer) ................................................................................................. 30
Figure-15 Transmit Differential Line Interface with Twisted Pair Cable (transformer-less, non standard compliant) .................................................. 30
Figure-16 Jitter Attenuator ........................................................................................................................................................................................... 32
Figure-17 LLOS Indication on Pins .............................................................................................................................................................................. 34
Figure-18 TLOS Detection Between Two Channels .................................................................................................................................................... 36
Figure-19 Pattern Generation (1) ................................................................................................................................................................................. 38
Figure-20 Pattern Generation (2) ................................................................................................................................................................................. 38
Figure-21 PRBS / ARB Detection ................................................................................................................................................................................ 39
Figure-22 IB Detection ................................................................................................................................................................................................. 40
Figure-23 Automatic Error Counter Updating .............................................................................................................................................................. 41
Figure-24 Manual Error Counter Updating .................................................................................................................................................................. 41
Figure-25 Priority Of Diagnostic Facilities During Analog Loopback ........................................................................................................................... 42
Figure-26 Priority Of Diagnostic Facilities During Manual Remote Loopback ............................................................................................................. 43
Figure-27 Priority Of Diagnostic Facilities During Digital Loopback ............................................................................................................................ 44
Figure-28 G.772 Monitoring ......................................................................................................................................................................................... 45
Figure-29 Automatic JM Updating ............................................................................................................................................................................... 46
Figure-30 Manual JM Updating ................................................................................................................................................................................... 46
Figure-31 Interrupt Service Process ............................................................................................................................................................................ 50
Figure-32 Reset ........................................................................................................................................................................................................... 51
Figure-33 1+1 HPS Scheme, Differential Interface (Shared Common Transformer) .................................................................................................. 53
Figure-34 1:1 HPS Scheme, Differential Interface (Individual Transformer) ............................................................................................................... 54
Figure-35 1+1 HPS Scheme, E1 75 ohm Single-Ended Interface (Shared Common Transformer) ........................................................................... 55
Figure-36 JTAG Architecture ....................................................................................................................................................................................... 95
Figure-37 JTAG State Diagram ................................................................................................................................................................................... 96
Figure-38 Transmit Clock Timing Diagram ................................................................................................................................................................ 109
Figure-39 Receive Clock Timing Diagram ................................................................................................................................................................. 109
Figure-40 CLKE1 Clock Timing Diagram ................................................................................................................................................................... 110
Figure-41 E1 Jitter Tolerance Performance ............................................................................................................................................................... 112
Figure-42 T1/J1 Jitter Tolerance Performance .......................................................................................................................................................... 112
Figure-43 E1 Jitter Transfer Performance ................................................................................................................................................................. 113
Figure-44 T1/J1 Jitter Transfer Performance ............................................................................................................................................................. 113
Figure-45 Read Operation in Serial Microprocessor Interface .................................................................................................................................. 114
Figure-46 Write Operation in Serial Microprocessor Interface ................................................................................................................................... 114
Figure-47 Timing Diagram ......................................................................................................................................................................................... 115
Figure-48 JTAG Timing ............................................................................................................................................................................................. 116
List of Figures
7
December 17, 2009