SI5010 ETC, SI5010 Datasheet
SI5010
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SI5010 Summary of contents
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... Board Level Serial Links Description The Si5010 is a fully integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data rates. DSPLL™ technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance in the application ...
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Preliminary Rev. 0.31 ...
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... Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DSPLL™ PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Preliminary Rev. 0.31 Si5010 Page 3 ...
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Detailed Block Diagram ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The Si5010 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 8. V ...
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Table 2. DC Characteristics (V = 2.5 V ± 5 –40°C to 85° Parameter Supply Current OC-12 OC-3 Power Dissipation OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK) Input Voltage Range* (DIN+, ...
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... GEN(PP) J OC-12 Mode BW OC-3 Mode J f < 2 MHz P T After falling edge of AQ PWRDN/CAL From the return of valid data C DUTY C TOL LOL LOCK Preliminary Rev. 0.31 Si5010 Min Typ Max Unit .15 — 666 MHz — 100 TBD ps — 100 TBD ps — 890 TBD ps — ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient High Speed Serial Input System Reference Clock Figure 5. Si5010 Typical Application Circuit 8 Symbol Value V –0 –0.3 to 3.6 DIG V – ...
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... SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. Jitter Tolerance The Si5010’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 6. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device ...
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... Device Grounding of jitter RMS The Si5010 uses the GND pad on the bottom of the 20-pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location. ...
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... Differential Input Circuitry The Si5010 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 8. In applications where direct DC coupling is possible, the 0.1 F capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6 ...
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... VDD Top View Figure 10. Si5010 Pin Configuration Table 8. Si5010 Pin Descriptions I/O Signal Level External Bias Resistor. This resistor is used by onboard circuitry to estab- lish bias currents within the device. This pin must be connected to GND through tor. 2.5 V Supply Voltage. ...
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... Table 8. Si5010 Pin Descriptions (Continued) Pin # Pin Name I/O 12, 13 DOUT–, O DOUT+ 15 PWRDN/CAL I 16, 17 CLKOUT–, O CLKOUT+ 19 RATESEL Signal Level CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN phase aligned with CLKOUT and is updated on the rising edge of CLKOUT ...
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... Ordering Guide Part Number Si5010-BM 14 Table 9. Ordering Guide Package Temperature 20-pin MLP –40°C to 85°C Preliminary Rev. 0.31 ...
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... Package Outline Figure 11 illustrates the package details for the Si5010. Table 10 lists the values for the dimensions shown in the illustration VIEW ...
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Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in ...