TDA10045 Philips Semiconductors, TDA10045 Datasheet - Page 5

• Manufacturer Part Number: TDA10045
• Description: DVB-T channel receiver
• Manufacturer: Philips Semiconductors

Philips Semiconductors
PINNING
2001 Nov 08
V
V
DS_SPARE3
VAGC
SCL_EEP
V
V
SDA_EEP
SCL_TUN
SDA_TUN
SCL
SDA
n.c.
CLR#
EEPADDR
SADDR[1:0]
V
V
TM[3:0]
SCAN_EN
V
V
DWNLOAD
SP_IN[1:0]
DDD33
SSD
DDD33
SSD
DDD18
SSD
DDD50
SSD
DVB-T channel receiver
SYMBOL
16 and 17
28 and 29
20 to 23
PIN
10
11
12
13
14
15
18
19
24
25
26
27
1
2
3
4
5
6
7
8
9
TYPE
OD
I/OD
I/OD
I/OD
I
I
I
I
I
I
I
I
O
O
O
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V
spare delta-sigma output; managed by the DSP to generate an analog level
(after a RC low-pass filter)
output value from the Delta-Sigma modulator, used to control a log-scaled
amplifier (after analog filtering)
extra I
mode); can be connected to the master I
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V)
extra I
(optional mode). It can be connected to the master I
open-drain which requires an external pull-up resistor (to V
even if not used.
tuner I
is open-drain which requires an external pull-up resistor (to V
even if not used
tuner I
is open-drain which requires an external pull-up resistor (to V
even if not used
I
I
external pull-up resistor (to V
not connected
asynchronous reset signal; active LOW
EEPADDR is the LSB of the I
internally set to 101000. Therefore the complete I
EEPROM is (MSB to LSB): 1, 0, 1, 0, 0, 0, EEPADDR.
SADDR[1:0] are the 2 LSBs of the I
are internally set to 00010; therefore the complete I
TDA10045 is (MSB to LSB): 0, 0, 0, 1, 0, SADDR[1] and SADDR[0]
digital supply voltage for the core (1.8 V typ.)
digital ground supply (0 V)
test mode bus; for test purpose; must be set to ‘0000’
scan enable for production test; connected to GND
digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if the 5 V
tolerant I/O is not required
digital ground supply (0 V)
processor control, boot mode; if set to logic 0, the DSP downloads the software
from an external EEPROM on the dedicated I
SCL_EEP). If set to logic 1 the software is downloaded in the I
CODE_IN from the host; in this case the external EEPROM is not needed.
spare inputs
2
2
C-bus master serial clock; up to 700 kbit/s
C-bus master serial data input/output, open-drain I/O pad, which requires an
2
2
2
2
C-bus clock to download DSP code from an external EEPROM (optional
C-bus data bus to download DSP code from an external EEPROM
C-bus serial clock signal; this signal is derived from the master SCL and
C-bus serial data signal; this signal is derived from the master SDA and
5
DDD33
2
C-bus address of the EEPROM. The MSBs are
DESCRIPTION
or V
2
C-bus address of the TDA10045; the MSBs
DDD50
2
C-bus
)
2
C-bus (pins SDA_EEP and
2
C-bus address of the
2
2
C-bus address of the
C-bus; this pin is
DDD33
TDA10045H
Product specification
DDD33
DDD33
2
C-bus register
or V
or V
or V
DDD50
DDD50
DDD50
),
),
),