TDA10045 Philips Semiconductors, TDA10045 Datasheet - Page 6

• Manufacturer Part Number: TDA10045
• Description: DVB-T channel receiver
• Manufacturer: Philips Semiconductors

Philips Semiconductors
2001 Nov 08
FFT_WIN
V
V
SACLK
FI[9:5]
V
V
FI[4:0]
V
V
IT
FEL
n.c.
n.c.
TRSTN
TMS
TDI
TCK
TDO
V
V
DS_SPARE2
DS_SPARE1
V
V
UNCOR
PSYNC
DDD33
SSD
DDD18
SSD
DDD50
SSD
DDD18
SSD
DDD33
SSD
DVB-T channel receiver
SYMBOL
34 to 38
41 to 45
PIN
30
31
32
33
39
40
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TYPE
OD
OD
I/O
I/O
I
I
I
I
IO
O
O
O
O
O
O
(2)
(2)
(2)
(2)
(1)
(1)
output or input signal indicating the start of the active data; equals 1 during
complex sample 0 of the active FFT block; can be used to synchronize 2 chips
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V)
sampling frequency output; this output clock can be fed to an external (10-bit)
ADC as a sampling clock; SACLK can also provide twice the sampling clock
input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
extra demodulator output signals (constellation or frequency response).
digital supply voltage for the core (1.8 V typ.)
digital ground supply (0 V)
input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
extra demodulator output signals (constellation or frequency response).
digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if 5 V tolerant
I/O is not required
digital ground supply (0 V)
interrupt line; this output interrupt line can be configured by the I
interface. This pin is an open-drain output and therefore requires an external
pull-up resistor (to V
front-end lock; FEL is an open-drain output and therefore requires an external
pull-up resistor (to V
not connected
not connected
asynchronous reset signal for boundary scan; connected to GND if not used
mode programming signal for boundary scan; connected to GND if not used
input port for boundary scan; connected to GND if not used
clock signal for boundary scan; connected to GND if not used)
output port for boundary scan; not connected if not used
digital supply voltage for the core (1.8 V typ.)
digital ground supply (0 V)
spare delta-sigma output; managed by the DSP or by an I
generate an analog level (after a RC low-pass filter)
spare delta-sigma output; managed by the DSP to handle a low frequency DAC
(automatic first stage tuner AGC measurement or 2nd AGC loop control as
examples)
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V)
RS error flag, active HIGH on one RS packet if the RS decoder fails to correct
the errors
pulse synchro; this output signal goes HIGH on a rising edge of OCLK when a
synchro byte is provided, then goes LOW until the next synchro byte
512 to +511). In internal ADC mode, these outputs can be used to monitor
512 to +511). In internal ADC mode, these outputs can be used to monitor
DDD33
DDD33
6
or V
or V
DDD50
DDD50
DESCRIPTION
).
)
2
C-bus register to
TDA10045H
Product specification
2
C-bus