TDA1311AT Philips Semiconductors, TDA1311AT Datasheet - Page 5

• Manufacturer Part Number: TDA1311AT
• Description: Stereo Continuous Calibration DAC CC-DAC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (see Fig.3a) transistor M1 is connected as a diode
by applying a reference current. The voltage V
intrinsic gate-source capacitance C
determined by the transistor characteristics. After
calibration of the drain current to the reference value I
the switch S1 is opened and S2 is switched to the other
position (see Fig.3b). The gate-to-source voltage V
M1 is not changed because the charge on C
preserved. Therefore, the drain current of M1 will still be
equal to I
available at the OUT terminal.
The 32 current sources and the spare current source of the
TDA1311A; AT are continuously calibrated (see Fig.1).
The spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors.
1995 Dec 18
handbook, full pagewidth
Stereo Continuous Calibration DAC
(CC-DAC)
(a) = calibration.
(b) = operation.
REF
and this exact duplicate of I
S1
C gs
(a)
gs
of M1 is then
V gs
out
REF
gs
is now
Fig.3 Calibration principle.
M1
gs
is
S2
on the
I ref
gs
REF
of
,
5
A symmetrical offset decoding principle is incorporated
that arranges the bit switching in such a way that the
zero-crossing is performed only by switching the LSB
currents.
The TDA1311A; AT (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in Figs 4
and 5.
With a HIGH level on the word select input (WS), data is
placed in the left input register and with a LOW level on the
WS input, data is placed in the right input register (see
Fig.1). The data in the input registers are simultaneously
latched in the output registers which control the bit
switches.
An internal offset voltage V
output voltage V
V
DD1
S1
C gs
/V
DD2
(b)
= V
V gs
FS1
I ref
out
FS
/V
; V
FS2
M1
OS
S2
= V
and V
I ref
MBG860
OS1
OS
is added to the full scale
FS
/V
OS2
are proportional to V
Preliminary specification
.
TDA1311A
DD
: