74ALVC16245 Fairchild Semiconductor, 74ALVC16245 Datasheet
74ALVC16245
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74ALVC16245 Summary of contents
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... The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The 74ALVC16245 is designed for low voltage (1.65V to 3.6V) V applications with I/O compatibility up to 3.6V. CC ...
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Connection Diagrams Pin Assignment of TSSOP Pin Assignment for FBGA (Top Thru View) Logic Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n T/R Transmit/Receive Input n A –A Side A Inputs or 3-STATE Outputs ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 5) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter V 3.3V CC Min Propagation Delay 1.3 PHL PLH Output Enable Time 1.3 PZL PZH Output Disable Time 1.3 PLZ PHZ Capacitance Symbol Parameter C Input ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...
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Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...