74ALVC162244TX Fairchild Semiconductor, 74ALVC162244TX Datasheet

74ALVC162244TX

Manufacturer Part Number

74ALVC162244TX

Description

IC BUFF DVR 16BIT LOW V 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Datasheet

1.74ALVC162244TX.pdf (8 pages)

Specifications of 74ALVC162244TX

Logic Type

Buffer/Line Driver, Non-Inverting

Number Of Elements

Number Of Bits Per Element

Current - Output High, Low

12mA, 12mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC162244GX

(Note 2)

74ALVC162244T

(Note 3)

74ALVC162244

Low Voltage 16-Bit Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

and 26 Series Resistor in Outputs

General Description

The ALVC162244 contains sixteen non-inverting buffers

with 3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

The 74ALVC162244 is designed for low voltage (1.65V to

3.6V) V

74ALVC162244 is also designed with 26

in the outputs. This design reduces line noise in applica-

tions such as memory address drivers, clock drivers, and

bus transceivers/transmitters.

The 74ALVC162244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Order Number

applications with I/O capability up to 3.6V. The

Package Number

BGA54A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

series resistors

DS500696

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

1.65V to 3.6V V

3.6V tolerant inputs and outputs

26 series resistors in outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

3.8 ns max for 3.0V to 3.6V V

4.3 ns max for 2.3V to 2.7V V

7.6 ns max for 1.65V to 1.95V V

Human body model

Machine model

Package Description

supply operation

200V

2000V

through a pull-up resistor; the minimum

November 2001

Revised November 2001

www.fairchildsemi.com

Related parts for 74ALVC162244TX

74ALVC162244TX Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation Features 1.65V to 3.6V V supply operation CC 3 ...

Page 2

Logic Symbol Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW –I Inputs –O Outputs ...

Page 3

Functional Description The 74ALVC162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) con- trolled with each nibble functioning identically, but indepen- dent of each other. The control pins may be shorted together to obtain full ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 5) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 5

AC Electrical Characteristics Symbol Parameter V 3.3V CC Min Propagation Delay 1.3 PHL PLH Output Enable Time 1.3 PZL PZH Output Disable Time 1.3 PLZ PHZ Capacitance Symbol Parameter C Input ...

Page 6

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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