74ALVC16601 Fairchild Semiconductor, 74ALVC16601 Datasheet

74ALVC16601

Manufacturer Part Number

74ALVC16601

Description

Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74ALVC16601.pdf (8 pages)

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74ALVC16601GX

(Note 2)

74ALVC16601MTD

(Note 3)

74ALVC16601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16601 is an 18-bit universal bus transceiver

which combines D-type latches and D-type flip-flops to

allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. When OEAB is LOW, the outputs are active. When

OEAB is HIGH, the outputs are in the high-impedance

state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

The ALVC16601 is designed for low voltage (1.65V to

3.6V) V

The ALVC16601 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

applications with I/O capability up to 3.6V.

Package Number

(Preliminary)

BGA54A

MTD56

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500682

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

1.65V–3.6V V

3.6V tolerant inputs and outputs

Power-down high impedance inputs and outputs

Supports live insertion/withdrawal (Note 1)

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

3.4 ns max for 3.0V to 3.6V V

4.0 ns max for 2.3V to 2.7V V

7.0 ns max for 1.65V 1.95V V

Human body model

Machine model 200V

(A to B, B to A)

Package Description

supply operation

2000V

through a pull-up resistor; the minimum

October 2001

Revised October 2001

www.fairchildsemi.com

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74ALVC16601 Summary of contents

Page 1

... BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2) (Preliminary) [TAPE and REEL] 74ALVC16601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 8) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 5

AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PLH 1.3 Bus to Bus Propagation Delay PHL PLH 1.3 CLK to Bus Propagation ...

Page 6

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-inverting ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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