CY7C4245-15JXC Cypress Semiconductor Corp, CY7C4245-15JXC Datasheet - Page 14

• Manufacturer Part Number: CY7C4245-15JXC
• Description: IC SYNC FIFO MEM 4KX18 68-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245-15JXC

• Access Time: 10ns
• Memory Size: 72K (4K x 18)
• Package / Case: 68-PLCC
• Function: Synchronous
• Data Rate: 100MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 4 K x 18
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 45 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Waveforms
Notes:
Document Number: 001-45652 Rev. **
24. PAE offset − n. Number of data words into FIFO already = n.
25. PAE offset − n.
26. t
27. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
and the rising RCLK is less than t
SKEW3
PAE
WEN
WCLK
WCLK
RCLK
RCLK
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
WEN
REN
REN
PAE
[24]
Figure 14. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
t
CLKH
SKEW3
(continued)
, then PAE may not change state until the next RCLK.
t
SKEW3
Figure 13. Programmable Almost Empty Flag Timing
t
CLKH
t
ENS
[26]
t
ENH
t
CLKL
Note 25
t
ENS
t
ENH
t
t
PAEsynch
CLKL
t
PAE
t
t
ENS
ENS
n+1 WORDS
N + 1 WORDS
IN FIFO
INFIFO
t
ENS
t
PAE
t
ENH
CY7C4425/4205/4215
CY7C4225/4235/4245
n WORDS IN FIFO
Note 27
t
PAEsynch
Page 14 of 22
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