HT48R03 Holtek Semiconductor, HT48R03 Datasheet
HT48R03
Related parts for HT48R03
HT48R03 Summary of contents
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... General Description The HT48R01/HT48R02/HT48R03 are 8-bit high per- formance, RISC architecture microcontroller devices specifically designed for I/O control. The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, Power-down and Selection Table ...
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... Block Diagram Pin Assignment Rev. 1.00 HT48R01/HT48R02/HT48R03 2 December 20, 2006 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 HT48R01/HT48R02/HT48R03 Description 12MHz, 8MHz and 4MHz. +6.0V Storage Temperature ...
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... Input High Voltage (PA7/RES) IH2 V Low Voltage Reset 1 LVR1 V Low Voltage Reset 2 LVR2 V Low Voltage Reset 3 LVR3 I I/O Port Sink Current OL I I/O Port Source Current OH R Pull-high Resistance PH Rev. 1.00 HT48R01/HT48R02/HT48R03 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS f =12MHz 4.5 SYS 3V No load, f =4MHz ...
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... Interrupt Pulse Width INT t Low Voltage Width to Reset LVR VDD Start Voltage to Ensure V POR Power-on Reset VDD Rise Rate to Ensure R POR Power-on Reset Note: t =1/f , 1/f or 1/f SYS SYS1 SYS2 SYS3 Rev. 1.00 HT48R01/HT48R02/HT48R03 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 4.5V~5.5V 400 4.5V~ 10800 12MHz, Ta=25 C 5.5V 3.3V~ 8MHz, Ta=25 C 7200 5.5V 2.2V~ 3600 4MHz, Ta= ...
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... Note: *11~*0: Program Counter bits #11~#0: Instruction code bits For HT48R01, the Program Counter is 10 bits wide, i.e. from *9~*0 For HT48R02, the Program Counter is 11 bits wide, i.e. from *10~*0 For HT48R03, the Program Counter is 12 bits wide, i.e. from *11~*0 Rev. 1.00 HT48R01/HT48R02/HT48R03 incremented by one. The program counter then points to the memory word containing the next instruction code ...
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... Note: *11~*0: Table location bits @7~@0: Table pointer bits For the HT48R01, the table address location is 10 bits, i.e. from *9~*0 For the HT48R02, the table address location is 11 bits, i.e. from *10~*0 For the HT48R03, the table address location is 12 bits, i.e. from *11~*0 Rev. 1.00 HT48R01/HT48R02/HT48R03 Location 008H This location is reserved for the Timer/Event Counter 0 interrupt service program ...
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... The general purpose data memory, addressed from 20H to 5FH (HT48R01), 20H to 7FH (HT48R02) or 20H to BFH (HT48R03), is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly ...
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... set by a WDT time-out. 6~7 Unused bit, read as 0 Rev. 1.00 HT48R01/HT48R02/HT48R03 RAM Mapping will not change the TO or PDF flag. In addition opera- tions related to the status register may give different re- sults from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction ...
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... SP is decre- mented. If immediate service is desired, the stack must be prevented from becoming full. Rev. 1.00 HT48R01/HT48R02/HT48R03 Function CTRL (16H) Register All these kinds of interrupts have a wake-up capability interrupt is serviced, a control transfer occurs by ...
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... T0F Internal timer/event counter 0 request flag (1= active; 0= inactive) 5 T1F Internal timer/event counter 1 request flag (1= active; 0= inactive) 7 Unused bit, read as 0 INTC 0 (0BH) Register for HT48R02/HT48R03 Rev. 1.00 HT48R01/HT48R02/HT48R03 Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Interrupt Subroutine Vector for HT48R02/HT48R03 ...
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... HALT Instruction CLKMOD During run state (HALT not execute) During run state (HALT execute) Rev. 1.00 HT48R01/HT48R02/HT48R03 Watchdog Timer - WDT The WDT clock source may come from a dedicated RC oscillator (WDT oscillator), RTC clock or instruction clock (system clock divided by 4) which is determined by option. This timer is designed to prevent a software mal- function or sequence from jumping to an unknown loca- tion with unpredictable results ...
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... Label Function Bit3~0, WDTEN3~WDTEN0= 1010B: WDT disable WDTEN0~ others: enable (using 0101B to 0~3 WDTEN3 enable WDT is strongly recom- mended for the highest noise im- munity) 4~5 Unused bit, read as 0 Rev. 1.00 HT48R01/HT48R02/HT48R03 Watchdog Timer Bit No. Label 1:1 1:2 INTES0~ 6~7 INTES1 1:4 1:8 1:16 WCON (17H) Register 1:32 Power Down Operation - HALT ...
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... Any wake-up from HALT will en- able the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out during normal mode or RES reset). Rev. 1.00 HT48R01/HT48R02/HT48R03 The functional unit chip reset status are shown below. Program Counter (system clock Interrupt Prescaler ...
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... PAWK -000 0000 CTRL -0-- 0000 WCON 10-- 1010 Note: * means warm reset - not implement u means unchanged x means unknown Rev. 1.00 HT48R01/HT48R02/HT48R03 RES Reset (Normal Operation) 000H 000H 1uuu uuuu -uuu uuuu 1uuu uuuu -uuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ...
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... TMR0 (TMR1). The counting is based on the f clock. INT Timer/Event Counter 1 - HT48R02/HT48R03 only Rev. 1.00 HT48R01/HT48R02/HT48R03 In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH ...
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... T1M1 11=Pulse width measurement mode 00=Unused Rev. 1.00 HT48R01/HT48R02/HT48R03 sults in a counting error, this must be taken into consid- eration by the programmer. The bit 0~2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The timer/event counter overflow signals can be used to generate signals for the buzzer ...
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... Each bit of these in- put/output latches can be set or cleared by SET [m].i Rev. 1.00 HT48R01/HT48R02/HT48R03 CLR [m].i (m=12H) instructions. Some instruc- tions first input data and then follow the output opera- tions. For example, SET [m].i , CLR [m].i , CPL [m] , ...
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... Since the low voltage has to be maintained in its original state and exceed t the reset mode. Rev. 1.00 HT48R01/HT48R02/HT48R03 Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0 ...
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... Internal RC frequency selection: 4MHz, 8MHz or 12MHz 3 WDT function: enable or disable 4 WDT clock source: WDTOSC CLRWDT instruction(s): one or two clear WDT instruction(s) 6 LVR function: enable or disable 7 LVR selection: 2.1V/3.15V/4.2V 8 RES or PA7 input selection Rev. 1.00 HT48R01/HT48R02/HT48R03 Options /4 or RTC OSC SYS 20 December 20, 2006 ...
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... The function of the resistor ensure that the oscillator will switch off should low voltage condi- tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Rev. 1.00 HT48R01/HT48R02/HT48R03 W C1, C2 35pF ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 HT48R01/HT48R02/HT48R03 Description 22 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT48R01/HT48R02/HT48R03 Description 23 Instruction Flag Cycle Affected 2 None (2) 1 ...
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... Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 addr ...
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... Affected flag(s) TO PDF 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 Program Counter addr OV ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 Program Counter+1 OV ...
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... Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 Stack Stack Stack OV Z ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 [m].i; [m].i:bit i of the data memory (i=0~ ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 ([m]+1) ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Note that this instruction is not valid for HT48R05A-1/HT48C05 Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1.00 HT48R01/HT48R02/HT48R03 ...
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... Package Information 10-pin MSOP Outline Dimensions Symbol Rev. 1.00 HT48R01/HT48R02/HT48R03 Dimensions in mm Min. Nom. 0 0.75 0.17 3 4.9 3 0.5 0.4 0. Max. 1.1 0.15 0.95 0.27 0.25 0.8 8 December 20, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT48R01/HT48R02/HT48R03 38 December 20, 2006 ...