HT48R03 Holtek Semiconductor, HT48R03 Datasheet - Page 13

• Manufacturer Part Number: HT48R03
• Description: (HT48R01 - HT48R03) 10-Pin MSOP I/O Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

The WDT overflow under normal operation will initialise
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialise a warm reset ,
and only the Program Counter and SP are reset to zero.
To clear the contents of WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a HALT in-
struction. The software instruction include CLR WDT
and the other set
these two types of instruction, only one can be active de-
pending on the option
tion . If the CLR WDT is selected (i.e. CLRWDT times
equal one), any execution of the CLR WDT instruction
will clear the WDT. In the case that CLR WDT1 and
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of time-out.
The WDT control register contains 4 bits of WDT enable
bits. WDT can be enable by either WDT mask option or
WDT control register (WDTEN[3:0]=0101B) and be dis-
able by both being disable.
Rev. 1.00
Bit No.
CLR WDT2 are chosen (i.e. CLRWDT times equal
0~3
4~5
WS2
0
0
0
0
1
1
1
1
WDTEN0~
WDTEN3
Label
WS1
0
0
1
1
0
0
1
1
CLR WDT1 and CLR WDT2 . Of
Bit3~0, WDTEN3~WDTEN0=
1010B: WDT disable
others: enable (using 0101B to
enable WDT is strongly recom-
mended for the highest noise im-
munity)
Unused bit, read as 0
CLR WDT times selection op-
WS0
0
1
0
1
0
1
0
1
Function
Division Ratio
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
Watchdog Timer
13
Power Down Operation - HALT
The HALT mode is initialised by the HALT instruction
and results in the following...
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialisation and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the CLR WDT instruction and is set when execut-
ing the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the Program Counter and Stack Pointer; the others keep
their original status.
Both port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it is awakened by an interrupt, two sequences
may happen. If the related interrupt is disabled or the in-
terrupt is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, the regular interrupt
response takes place. If an interrupt request flag is set to
Bit No.
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
6~7
HT48R01/HT48R02/HT48R03
INTES0~
INTES1
Label
WCON (17H) Register
External interrupt edge selection
(default=10)
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Function
December 20, 2006