HT48R03 Holtek Semiconductor, HT48R03 Datasheet - Page 10

• Manufacturer Part Number: HT48R03
• Description: (HT48R01 - HT48R03) 10-Pin MSOP I/O Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
System Control Register
Note: For the HT48R01, BZCS is always 0 no matter what value is written into it; i.e., clock source for Buzzer is only
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control Reg-
ister (INTC;0BH) contains the interrupt control bits to set
the enable or disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, by clearing the EMI bit. This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain in-
terrupt requires servicing within the service routine, the
EMI bit and the corresponding bit in the INTC register
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decre-
mented. If immediate service is desired, the stack must
be prevented from becoming full.
Rev. 1.00
Bit No.
4~5
0
1
2
3
6
7
from timer0.
CLKMOD
BZEN0
BZEN1
QOSC
BZCS
Label
Clock mode selection - select the system clock source
0: High speed clock as system clock - internal RC
1: Low speed clock as system clock - 32.768kHz, and RC oscillator stop
Note: This selection is used only in internal RC + RTC mode.
32768Hz OSC quick start-up oscillating setting
0: quickly startup
1: slow startup
BZ/BZ enable/disable
00: both disabled
01: Reserved
10: BZ only enabled
11: BZ and BZ enabled
When BZ or BZ are disabled, the I/O port will have general I/O functions. If enabled, the BZ or
BZ outputs will still be controlled by the related I/O port control and data settings. Refer to the
I/O chapter for details.
Unused bit, read as 0
BZCS, buzzer clock source, 0/1: Timer0/Timer1
Unused bit, read as 0
CTRL (16H) Register
10
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
are altered by the interrupt service program which cor-
rupts the desired control sequence, the contents should
be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC) will be set. When the interrupt is enabled, the
stack is not full and the external interrupt is active, a sub-
routine call to location 04H will occur. The interrupt re-
quest flag (EIF) and EMI bits will be cleared to disable
other interrupts.
Function
HT48R01/HT48R02/HT48R03
December 20, 2006