HT48R70A-1 Holtek Semiconductor Inc, HT48R70A-1 Datasheet
HT48R70A-1
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HT48R70A-1 Summary of contents
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... Watchdog Timer General Description The HT48R70A-1/HT48C70-1 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48C70-1 is fully pin and functionally compatible with the OTP version HT48R70A-1 device ...
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... Block Diagram Rev. 1.60 HT48R70A-1/HT48C70-1 2 June 9, 2004 ...
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... Pin Assignment Rev. 1.60 HT48R70A-1/HT48C70-1 3 June 9, 2004 ...
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... Pad Assignment HT48C70-1 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.60 HT48R70A-1/HT48C70-1 4 June 9, 2004 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.60 HT48R70A-1/HT48C70-1 Description +6.0V Storage Temperature ............................ 125 ...
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... V Input Low Voltage (RES) IL2 V Input High Voltage (RES) IH2 V Low Voltage Reset LVR I I/O Port Sink Current OL I I/O Port Source Current OH R Pull-high Resistance PH Rev. 1.60 HT48R70A-1/HT48C70-1 Test Conditions Min. Typ. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V 0.6 No load, f =4MHz SYS ...
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... Watchdog Time-out Period (System Clock) WDT2 t Watchdog Time-out Period (RTC OSC) WDT3 t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT Rev. 1.60 HT48R70A-1/HT48C70-1 Test Conditions Min. Typ. Max. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 400 3.3V~5.5V 400 3.2MHz 1800 1 ...
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... S12 S11 S10 Note: *12~*0: Program counter bits #12~#0: Instruction code bits Rev. 1.60 HT48R70A-1/HT48C70-1 incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading register, subroutine call or return from ...
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... Note: *12~*0: Table location bits @7~@0: Table pointer bits Rev. 1.60 HT48R70A-1/HT48C70-1 Program Memory routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur ...
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... Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op- Rev. 1.60 HT48R70A-1/HT48C70-1 RAM Mapping eration of [00H] ([02H]) will access data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indi- rectly will return the result 00H. Writing indirectly results in no operation ...
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... WDT time-out Unused bit, read as 0 Rev. 1.60 HT48R70A-1/HT48C70-1 Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags ...
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... It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. In- Rev. 1.60 HT48R70A-1/HT48C70-1 Function INTC Register terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. ...
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... If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscil- lator (RTC OSC) is strongly recommended, since the HALT will stop the system clock. Rev. 1.60 HT48R70A-1/HT48C70-1 WS2 WS1 WS0 ...
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... WDT wake-up HALT Note: u stands for unchanged Rev. 1.60 HT48R70A-1/HT48C70-1 To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the sys- tem reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state ...
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... PGC 1111 1111 1111 1111 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.60 HT48R70A-1/HT48C70-1 RES Reset RES Reset WDT Time-out (Normal Operation) (HALT) xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ...
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... T1M1 7 11=Pulse width measurement mode 00=Unused Rev. 1.60 HT48R70A-1/HT48C70-1 There are 3 registers related to the Timer/Event Counter 0;TMR0H ([0CH]), TMR0L ([0DH]), TMR0C ([0EH]). Writ- ing TMR0L will only put the written data to an internal lower-order byte buffer (8 bits) and writing TMR0H will ...
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... T0ON/T1ON. The measured result will remain in the Timer/Event Counter 0/1 even if the activated transient occurs again. In other words, only Rev. 1.60 HT48R70A-1/HT48C70-1 one cycle measurement can be done. Until setting the T0ON/T1ON, the cycle measurement will function again as long as it receives further transient pulse. Note that, ...
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... If the control register bit the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. Rev. 1.60 HT48R70A-1/HT48C70-1 For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H, 1BH, 1DH and 1FH. ...
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... PA, PB, PC, PD, PE, PF, PG pull-high enable or disable (By port) System oscillator 8 Ext. RC, Ext. crystal, Int. RC+RTC 9 Int. RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz 10 LVR enable or disable Rev. 1.60 HT48R70A-1/HT48C70-1 The relationship between V and the voltage range for proper chip opera- Note: OPR tion at 4MHz system clock. ...
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... The function of the resistor ensure that the oscillator will switch off should low voltage condi- tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Rev. 1.60 HT48R70A-1/HT48C70 C1, C2 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.60 HT48R70A-1/HT48C70-1 Instruction Description 21 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.60 HT48R70A-1/HT48C70-1 Instruction Description 22 Flag Cycle Affected 2 None ...
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... Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Operation Stack PC+1 PC addr Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... PDF 0* 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation PC addr Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1.60 HT48R70A-1/HT48C70 ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions Symbol Min. A 395 B 291 613 Rev. 1.60 HT48R70A-1/HT48C70-1 Dimensions in mil Nom. Max. 420 299 12 637 June 9, 2004 ...
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... QFP (14´20) Outline Dimensions Symbol Min. A 18.80 B 13.90 C 24.80 D 19. 2. 1.15 K 0.10 0 Rev. 1.60 HT48R70A-1/HT48C70-1 Dimensions in mm Nom. Max. 19.20 14.10 25.20 20.10 1 0.40 3.10 3.40 0.10 1.45 0. June 9, 2004 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.60 HT48R70A-1/HT48C70-1 Dimensions in mm 330 1.0 100 0.1 13.0+0.5 0.2 2.0 0.5 32.2+0.3 0.2 38.2 0.2 38 June 9, 2004 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.60 HT48R70A-1/HT48C70-1 Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.1 14.2 0.1 2.0 Min. 1.5+0.25 4.0 0.1 2.0 0.1 12.0 0.1 16.20 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 39 June 9, 2004 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.60 HT48R70A-1/HT48C70-1 40 June 9, 2004 ...