HT48R70A-1 Holtek Semiconductor Inc, HT48R70A-1 Datasheet - Page 11

• Manufacturer Part Number: HT48R70A-1
• Description: I/O Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor Inc

Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the CLR WDT or HALT in-
struction. The PDF flag can be affected only by exe-
cuting the
during a system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Rev. 1.60
C
AC
Z
OV
PDF
TO
Labels
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
HALT
Bits
6, 7
0
1
2
3
4
5
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set
by a WDT time-out.
Unused bit, read as 0
C is set if the operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by exe-
cuting the HALT instruction.
or
CLR WDT
instruction or
Status Register
11
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable or disable and the interrupt request
flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related in-
terrupt is enabled, until the SP is decremented. If immedi-
ate service is desired, the stack must be prevented from
becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of the INT and the related interrupt request flag (EIF;
bit 4 of INTC) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of INTC), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
Function
HT48R70A-1/HT48C70-1
June 9, 2004