HT68F04 Holtek Semiconductor, HT68F04 Datasheet
HT68F04
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HT68F04 Summary of contents
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... Reset and Low Voltage Detector coupled with ex- cellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical envi- ronments. Rev. 1.00 HT66F03/ HT66F04/HT68F03/ HT68F04 Small Package Enhanced Flash Type 8-Bit MCU with EEPROM Peripheral Features · Flash Program Memory: 1K´14 ~ 2K´15 · ...
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... HT68F03 1K´14 64´8 64´8 5.5V 2.2V~ HT68F04 2K´15 96´8 64´8 5.5V Block Diagram Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Ext. Timer I/O A/D Comparator Int. Module 10-bit CTM´ 12-bit´4 10-bit STM´1 10-bit CTM´1, 10-bit ETM´ 12-bit´4 10-bit STM´1 10-bit CTM´ ...
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... Bracketed pin names indicate non-default pinout remapping locations the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the ²/² sign can be used for higher priority. 3. VDD&AVDD means the VDD and AVDD are the double bonding. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 3 www.DataSheet4U.com April 16, 2010 ...
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... VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 OP I/T O/T Pin-Shared Mapping PAWU ¾ ...
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... VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together in- ternally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 OP I/T O/T Pin-Shared Mapping PAWU ¾ ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 OP I/T O/T ...
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... SYS H S SUB LIRC Operating Current (HIRC), I DD3 ( SYS H S SUB LXR LIRC Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Test Conditions Min. V Conditions DD f =8MHz 2.2 SYS ¾ f =12MHz 2.7 SYS f =20MHz 4.5 SYS ¾ load, f =8MHz, H ADC off, WDT enable ¾ 5V ¾ ...
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... SYS S SUB LIRC Standby Current (Idle) (LXT), I STB7 ( SYS L LXT S SUB LXT Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Test Conditions Min. V Conditions DD ¾ load, f =12MHz / ADC off, WDT enable ¾ 5V ¾ load, f =12MHz / ADC off, WDT enable ¾ ...
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... LVD Voltage Level V LVD5 V LVD6 V LVD7 V LVD8 I LVD1 Additional Power Consumption if LVR and LVD is Used I LVD2 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Test Conditions Min. V Conditions DD ¾ load, system HALT, ADC off, WDT enable, ¾ =32768Hz SYS ¾ load, system HALT, ADC off, WDT enable, ¾ ...
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... Voltage Additional Power Consumption I if 1.25V Reference with Buffer is 125 used A.C. Characteristics Symbol Parameter f Operating Clock CPU f System Clock (HXT) SYS f System Clock (ERC) ERC Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Test Conditions Min. V Conditions DD ¾ =9mA OL ¾ =20mA 2.7 =-3.2mA 4.5 =-7 ...
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... External Reset Low Pulse Width RES t Interrupt Pulse Width INT t Low Voltage Width to Reset LVR t Low Voltage Width to Interrupt LVD t LVDO stable time LVDS t V Turn on Stable Time BGS 125 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Test Conditions Min. V Conditions DD -2% 3V/5V Ta=25°C -2% 3V/5V Ta=25°C -2% 5V Ta=25°C -5% 3V/5V Ta=0~70°C -5% 3V/5V Ta=0~70°C -5% 5V Ta=0~70°C 2 ...
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... ADC A/D Converter is Used t A/D Converter Clock Period ADCK A/D Conversion Time (Include t ADC Sample and Hold Time) t A/D Converter Sampling Time ADS t A/D Converter On-to-Start Time ON2ST Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Test Conditions Min. V Conditions DD ¾ f =XTAL or RTC OSC SYS ¾ f =ERC or HIRC OSC SYS ¾ ¾ ...
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... Parameter VDD Start Voltage to Ensure V POR Power-on Reset VDD Raising Rate to Ensure R POR AC Power-on Reset Minimum Time for VDD Stays at t POR V to Ensure Power-on Reset POR Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Test Conditions Min. V Conditions DD ¾ ¾ 2.2 ¾ ¾ 3V ¾ ¾ 5V ¾ ¾ ...
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... Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC, LIRC or ERC oscillator is subdivided into four in- Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ternally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions ...
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... If the stack is overflow, the first Program Counter save in the stack will be lost. Device Stack Levels HT66F03/HT68F03 HT66F04/HT68F04 Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic oper- ations of the instruction set. Connected to the main ...
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... After setting up the table pointer, the table data can be retrieved from the Program Memory using the Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ²TABRD[m]² or ²TABRDL[m]² instructions, respec- tively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as speci- fied in the instruction ...
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... Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two ad- ditional lines are required for the power supply and one line for the reset ...
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... HT68F03 HT66F04 40H~9FH 96´8 HT68F04 The second area of Data Memory is known as the Gen- eral Purpose Data Memory, which is reserved for gen- eral purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks for all the devices ...
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... HT66F04 Special Purpose Data Memory Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 HT68F03/HT68F04 Special Purpose Data Memory General Purpose Data Memory 19 www.DataSheet4U.com April 16, 2010 ...
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... The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are pro- vided. These Memory Pointers are physically imple- mented in the Data Memory and can be manipulated in the same way as normal registers providing a conve- nient way with which to address and track data ...
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... Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to pro- grammers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily imple- mented ...
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... C is also affected by a rotate through carry instruction. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 is also affected by a rotate through carry instruction. · set if an operation results in a carry out of the low nibbles in addition borrow from the high nib- ble into the low nibble in subtraction ...
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... Unimplemented, read as ²0² Bit Bit Data EEPROM address Data EEPROM address bit 5 ~ bit 0 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Device All devices EEPROM Registers Three registers control the overall operation of the inter- nal EEPROM Data Memory. These are the address reg- ister, EEA, the data register, EED and a single control register, EEC ...
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... Note: The WREN, WR, RDEN and RD can not be set to ²1² at the same time in one instruction. The WR and RD can not be set to ²1² at the same time. · EED Register Bit 7 6 Name D7 D6 R/W R/W R/W POR x x Bit Data EEPROM address Data EEPROM address bit 7 ~ bit 0 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ¾ WREN WR ¾ ¾ R/W R/W ¾ ¾ ...
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... EEPROM. The ap- plication program can therefore poll the WR bit to deter- mine when the write cycle has ended. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Write Protection Protection against inadvertent write operation is pro- vided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations ...
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... SET IAR1.2 BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ...
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... High Speed Oscillation HXT ERC HIRC High Speed Oscillation Configuration Option Low Speed Oscillation LIRC LXT Low Speed Oscillation Configuration Option Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Type Name External Crystal HXT External RC ERC Internal High HIRC Speed RC External Low LXT Speed Crystal ...
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... Using a ceramic resonator will usually require two small value capacitors, C1 and C2 connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer¢s specification. Crystal/Resonator Oscillator - HXT Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz 8MHz 4MHz 1MHz Note: C1 and C2 values are for guidance only ...
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... If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the OSC1 and OSC2 pins. External LXT Oscillator Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 LXT Oscillator C1 and C2 Values Crystal Frequency C1 32.768kHz 10pF Note and C2 values are for guidance only. ...
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... Thus there /64 for peripheral circuit to use Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 The main system clock, can come from either a high fre- quency low frequency using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT, ERC or HIRC oscillator, selected via a configuration option ...
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... However the f and f clocks will continue SUB S Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 istics and which can be chosen according to the specific clock is used performance and power requirements of the applica- tion. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode ...
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... HLCLK: system clock selection / This bit is used to select if the f clock. When the bit is high the f be selected. When system clock switches from the f be automatically switched off to conserve power. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 CKS0 FSTEN LTO HTO R/W R ...
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... Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 able function is controlled using the FSTEN bit in the SMOD register. ...
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... H H Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 sources will also stop running, which may affect the op- eration of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what hap- pens when the device moves between the various oper- ating modes ...
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... Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¹ Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the ²HALT² instruc- tion in the application program with the IDLEN bit in SMOD register equal to ² ...
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... In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ² ...
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... If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP0 Mode and both the HIRC and LXT oscillators need to start-up from an off state ...
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... WDTEN3, WDTEN2, WDTEN1, WDTEN0 : WDT Software Control 1010: Disable Other: Enable Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 However, it should be noted that this specified internal clock period can vary with VDD, temperature and pro- cess variations. The LXT oscillator is supplied by an ex- ternal 32.768kHz crystal. The other Watchdog Timer ...
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... Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset ...
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... Note power-on delay, typical time=100ms RSTD Power-On Reset Timing Chart Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 · RES Pin As the reset pin is shared with PB.0, the reset function must be selected using a configuration option. Al- though the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast ...
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... Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the WDT Time-out Reset during SLEEP or IDLE Timing Chart Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Program Counter and the Stack Pointer will be cleared to ²0² and the TO flag will be set to ²1². Refer to the A.C. Characteristics for t Note: ...
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... ADRH (ADRFS= ADCR0 ADCR1 - - - - ACERL Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 RES or LVR WDT Time-out Reset (Normal Operation ...
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... TM1AH ²u² stands for unchanged Note: ²x² stands for unknown ²-² stands for unimplemented Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 RES or LVR WDT Time-out Reset (Normal Operation ...
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... ACERL CPC TM0C0 TM0C1 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 RES or LVR WDT Time-out Reset (Normal Operation ...
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... TM2BL TM2BH ²u² stands for unchanged Note: ²x² stands for unknown ²-² stands for unimplemented Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 RES or LVR WDT Time-out Reset (Normal Operation ...
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... TM1AH ²u² stands for unchanged Note: ²x² stands for unknown ²-² stands for unimplemented Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 RES or LVR WDT Time-out Reset (Normal Operation ...
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... HT68F04 Register Reset Register (Power-on) MP0 MP1 ACC PCL TBLP TBLH - - - - - TBHP - - STATUS ...
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... Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. · PAWU Register Bit 7 6 Name D7 D6 R/W R/W R/W POR 0 0 Bit 7~0 PAWU: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Bit ...
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... However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. · Pin-remapping Register List Register Name 7 6 PRM PRML3 PRML2 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 R/W R/W R/W R/W ...
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... Within the user program, one of the first things to con- sider is port initialisation. After a reset, all of the I/O data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ...
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... Note also that as the A/D channel is enabled, any internal pull-high resistor connections will be re- moved. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins ...
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... TM0~TM2. Device HT66F03/HT68F03/HT68F04 HT66F04 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Introduction The devices contain from two to four TMs depending upon which device is selected with each TM having a reference name of TM0, TM1 and TM2. Each individual ...
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... As the Enhanced Device HT66F03/HT68F03/HT68F04 HT66F04 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions, it consequently has three internal interrupts. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM out- put pin ...
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... High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ¨ Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxBL - this step reads data from the 8-bit buffer. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 TM Counter Register (Read only) TMxDL TMxDH 8-bit Buffer ...
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... The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected us- ing relevant internal registers. Compact Type TM Block Diagram Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 TM No. TM Input Pin 0 TCK0 55 www ...
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... TM0AL Register Bit 7 6 Name D7 D6 R/W R/W R/W POR 0 0 Bit 7~0 TM0AL: TM0 CCRA Low Byte Register bit 7 ~ bit 0 TM0 10-bit CCRA bit 7 ~ bit 0 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Bit5 Bit4 Bit3 Bit2 T0CK1 T0CK0 T0ON T0RP2 T0IO1 T0IO0 T0OC T0POL ¾ ¾ ...
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... TM0 clocks 001: 128 TM0 clocks 010: 256 TM0 clocks 011: 384 TM0 clocks 100: 512 TM0 clocks 101: 640 TM0 clocks 110: 768 TM0 clocks 111: 896 TM0 clocks Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ¾ ¾ ¾ ¾ ...
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... Compare Match Output Mode or in the PWM Mode. It has no effect if the the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ...
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... Hex, value, however here the TnAF in- terrupt request flag will not be generated. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a com- pare match occurs from Comparator A ...
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... Compare Match Output Mode - TnCCLR = 0 Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TM output pin controlled only by TnAF flag 3. Output pin reset to initial state by TnON bit rising edge Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 60 www.DataSheet4U.com April 16, 2010 ...
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... Compare Match Output Mode - TnCCLR = 1 Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TM output pin controlled only by TnAF flag 3.TM output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 61 www.DataSheet4U.com April 16, 2010 ...
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... Internal PWM function continues even when TnIO1, TnIO0 = TnCCLR bit has no influence on PWM operation Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register ...
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... Note: 1. Here TnDPX = 1 - Counter cleared by CCRA 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1, TnIO0 = TnCCLR bit has no influence on PWM operation Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 PWM Mode - TnDPX = 1 63 www.DataSheet4U.com April 16, 2010 ...
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... TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur interrupt signal will Standard Type TM Block Diagram Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 TM No. TM Input Pin 1 TCK1 also usually be generated. The Standard Type TM can ...
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... If the the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Bit5 Bit4 Bit3 ...
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... PWM Mode/Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1 01: Input capture at falling edge of TP1 10: Input capture at falling/rising edge of TP1 11: Input capture disabled Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 T1IO1 T1IO0 T1OC T1POL R/W R/W ...
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... Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 67 www.DataSheet4U.com April 16, 2010 ...
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... TM1AH Register Bit 7 6 ¾ ¾ Name ¾ ¾ R/W ¾ ¾ POR Unimplemented, read as ²0² Bit 7~2 Bit 1~0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ...
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... TM output pin controlled only by TnAF flag 3. Output pin reset to initial state by TnON bit rising edge Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 from Comparator A. However, here only the TnAF inter- rupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. ...
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... Note: Points to note for above diagram: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TM output pin controlled only by TnAF flag 3.TM output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 70 www.DataSheet4U.com April 16, 2010 ...
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... Internal PWM function continues even when TnIO1, TnIO0 = TnCCLR bit has no influence on PWM operation Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period ...
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... Note: 1. Here TnDPX = 1 - Counter cleared by CCRA 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1, TnIO0 = TnCCLR bit has no influence on PWM operation Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 PWM Mode - TnDPX = 1 72 www.DataSheet4U.com April 16, 2010 ...
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... Pulse triggered by TCKn pin or setting TnON bit high 4. TCKn pin active edge will auto set TnON bit Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse out- put. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated ...
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... No output function - TnOC and TnPOL bits not used 5. CCRP sets counter maximum value Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 the CCRA registers and a TM interrupt generated. Irre- spective of what events occur on the TP1 pin the coun- ter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero ...
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... The CCRP comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while CCRA and CCRB are 10-bits wide and therefore com- pared with all counter bits. Enhanced Type TM Block Diagram Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Name TM No. TM Input Pin ¾ ¾ ...
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... TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Bit5 Bit4 Bit3 ...
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... Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 T2AIO1 T2AIO0 T2AOC ...
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... Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T2CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 78 www.DataSheet4U.com April 16, 2010 ...
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... Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 T2BIO1 ...
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... TM2AH Register Bit 7 6 ¾ ¾ Name ¾ ¾ R/W ¾ ¾ POR Unimplemented, read as ²0² Bit 7~2 Bit 1~0 TM2AH: TM2 CCRA High Byte Register bit 1~bit 0 TM210-bit CCRA bit 9~bit 8 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ...
Page 81
... Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt re- quest flags for Comparator A and Comparator P respec- tively, will both be generated. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ...
Page 82
... TPnA output pin controlled only by TnAF flag 3. Output pin reset to initial state by TnON bit rising edge Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB pins high low or to toggle from its present condi- tion when a compare match occurs from Comparator compare match occurs from Comparator B ...
Page 83
... ETM CCRB Compare Match Output Mode - TnCCLR = 0 Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TPnB output pin controlled only by TnBF flag 3. Output pin reset to initial state by TnON bit rising edge Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 83 www.DataSheet4U.com April 16, 2010 ...
Page 84
... ETM CCRA Compare Match Output Mode - TnCCLR = 1 Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TPnA output pin controlled only by TnAF flag 3. TPnA output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 84 www.DataSheet4U.com April 16, 2010 ...
Page 85
... ETM CCRB Compare Match Output Mode - TnCCLR = 1 Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TPnB output pin controlled only by TnBF flag 3. TPnB output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 85 www.DataSheet4U.com April 16, 2010 ...
Page 86
... B Duty Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 can be finely controlled using the CCRA registers. In this case the CCRB registers are used to set the PWM duty value (for TPnB output pin). The CCRP bits are not used and TPnA output pin is not used. The PWM output can only be generated on the TPnB output pin ...
Page 87
... Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period 2. Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0 CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 PWM Mode - Edge Aligned 87 www.DataSheet4U.com April 16, 2010 ...
Page 88
... Note: 1. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period 2. Internal PWM function continues even when TnBIO1, TnBIO0 = CCRA controls TPnB PWM period and CCRB controls TPnB PWM duty Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 PWM Mode - Edge Aligned 88 www.DataSheet4U.com April 16, 2010 ...
Page 89
... Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0 CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 PWM Mode - Centre Aligned 89 www.DataSheet4U.com ...
Page 90
... Internal PWM function continues even when TnBIO1, TnBIO0 = CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 PWM Mode - Centre Aligned 90 www.DataSheet4U.com ...
Page 91
... TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of ® Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be generated ...
Page 92
... TPnB Pin running internally TnBOC = 1 Pulse Width set by CCRA - CCRB TPnB Pin TnBOC = 0 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 TnAM1, TnAM0 and TnBM1, TnBM0 = 10; TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11 Pause Resume Software Trigger TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11 TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11 ...
Page 93
... TnCCLR bit not used 4. No output function - TnAOC and TnAPOL bits not used 5. CCRP sets counter maximum value Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator inter- rupt will also be generated ...
Page 94
... TnBM1, TnBM0 = 01 and active edge set by TnBIO1 and TnBIO0 bits 2. TM Capture input pin active edge transfers counter value to CCRB 3. TnCCLR bit not used 4. No output function - TnBOC and TnBPOL bits not used 5. CCRP sets counter maximum value Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Pause Active edges YY XX ...
Page 95
... D11 D10 D11 D10 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Input Part No. Channels HT66F03 4 HT66F04 The accompanying block diagram shows the overall in- ternal structure of the A/D converter, together with its as- sociated registers. A/D Converter Register Description Overall operation of the A/D converter is controlled us- ing six registers. A read only register pair exists to store the ADC data 12-bit value ...
Page 96
... ACS4, ACS1 and ACS0 bits to determine which analog channel input pins or internal 1.25V is actually con- nected to the internal A/D converter. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 The ACERL control register contains the ACER3~ ACER0 bits which determine which pins on Port A are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input ...
Page 97
... These are the A/D channel select control bits. As there is only one internal hardware A/D converter each of the four A/D inputs must be routed to the internal converter using these bits. If bit ACS4 in the ADCR1 register is set high, then the internal 1.25V reference voltage source will be routed to the A/D Converter. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ...
Page 98
... SYS 011 SYS 100: f /16 SYS 101: f /32 SYS 110: f /64 SYS 111: Undefined These three bits are used to select the clock source for the A/D converter. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ¾ VREFS ADCK2 ¾ ¾ R/W R/W ¾ ¾ www ...
Page 99
... A/D inter- nal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ¾ ...
Page 100
... Note that it is not necessary to first setup the A/D pin as an input in the PAC port control register to enable the A/D input as when the ACE3~ACE0 bits enable an A/D input, the status of the port control register will be overridden. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 A/D Clock Period (t ) ADCK ADCK2, ADCK2, ...
Page 101
... I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 The power-on reset condition of the A/D converter con- trol registers will ensure that the shared function pins are setup as A/D converter inputs. If any of the A/D con- ...
Page 102
... Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 A/D Conversion Timing Ideal A/D Transfer Function 102 www.DataSheet4U.com April 16, 2010 ...
Page 103
... EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 /8 as A/D clock and switch off 1.25V SYS /8 as A/D clock and switch off 1.25V SYS 103 www.DataSheet4U.com April 16, 2010 ...
Page 104
... The hysteresis function, if enabled, also increases the switching offset value. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Comparator Interrupt The comparator possesses its own interrupt function. When the comparator output changes state, its relevant interrupt flag will be set, and if the corresponding inter- rupt enable bit is set, then a jump to its relevant interrupt vector will be executed ...
Page 105
... On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ...
Page 106
... MFI1 register is reserved for advanced expansion recommended that do not access the MFI1 register and keep its initial setting to avoid malfunction. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ing convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an ²E² for en- able/disable bit or ² ...
Page 107
... R/W ¾ ¾ POR unimplemented, read as ²0² Bit 7~2 Bit 1~0 INTS1, INTS0: interrupt edge control for INT pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Bit ¾ ¾ CPF INTF MF0E CPE MF2F MF1F TB0E ADE ¾ ...
Page 108
... Bit 4 Bit 3 TB0E: Time Base 0 Interrupt Control 0: disable 1: enable Bit 2 ADE: A/D converter interrupt control 0: disable 1: enable Bit 1 MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable reserved and can not be used, read as ²0² Bit 0 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 CPF INTF MF0E CPE R/W R/W R/W R ...
Page 109
... Bit 4 Bit 3 TB0E: Time Base 0 Interrupt Control 0: disable 1: enable unimplemented, read as ²0² Bit 2 Bit 1 MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable reserved and can not be used, read as ²0² Bit 0 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 MF2F MF1F TB0E ADE R/W R/W R/W R ...
Page 110
... Bit 2 T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable Bit 1 T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable Bit 0 T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ ¾ ¾ TB1F ¾ ¾ ¾ R/W ¾ ¾ ...
Page 111
... Interrupt request Bit 4 LVF: LVD interrupt request flag 0: No request 1: Interrupt request unimplemented, read as ²0² Bit 3~2 Bit 1 DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 0 LVE: LVD Interrupt Control 0: Disable 1: Enable Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ¾ T2AF T2PF T2BE ¾ R/W R/W R/W ¾ ...
Page 112
... Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 The various interrupt enable bits, together with their as- sociated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector ...
Page 113
... T1AF T1AE TM0 P T0PF T0PE TM0 A T0AF T0AE EEPROM DEF DEE LVD LVF LVE Interrupts contained within Multi-Function Interrupts Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 EMI auto disabled in ISR Interrupt Request Enable Name Flags Bits INT Pin INTF INTE Comparator CPF CPE M. Funct. 0 MF0F MF0E M ...
Page 114
... T2PF T2PE TM2 A T2AF T2AE TM2 B T2BF T2BE DEF DEE EEPROM LVD LVF LVE Interrupts contained within Multi-Function Interrupts Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 EMI auto disabled in ISR Interrupt Request Enable Name Flags Bits INT Pin INTF INTE Comparator CPF CPE M. Funct. 0 MF0F MF0E M ...
Page 115
... T1AF T1AE TM0 P T0PF T0PE TM0 A T0AF T0AE EEPROM DEF DEE LVD LVF LVE Interrupts contained within Multi-Function Interrupts Interrupt Structure - HT68F03/HT68F04 Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 EMI auto disabled in ISR Interrupt Request Enable Master Name Flags Bits Enable INT Pin INTF INTE Comparator ...
Page 116
... TM Interrupts, SIM Interrupt, External Peripheral In- terrupt, LVD interrupt and EEPROM Interrupt. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an inter- rupt request flag ...
Page 117
... TB02~TB00: Select Time Base 0 Time-out Period 000: 256/f TB 001: 512/f TB 010: 1024/f TB 011: 2048/f TB 100: 4096/f TB 101: 8192/f TB 110: 16384/f TB 111: 32768/f TB Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 input clock passes through a divider, the division ratio of which is se TB11 TB10 LXTLP TB02 R/W R/W R/W R ¸ ...
Page 118
... TM request flags are set, a situa- tion which occurs when a TM comparator match situation happens. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, re- spective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set ...
Page 119
... CALL subroutine is exe- cuted in the interrupt subroutine. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Every interrupt has the capability of waking up the microcontroller when SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high ...
Page 120
... CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: · ...
Page 121
... Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage DD value. The LVDEN bit is used to control the overall on/off function of the low voltage detector ...
Page 122
... LVD LVDO transitions. LVD Operation Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function inter- rupts, providing an alternative means of low voltage de- tection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of t bit has been set high by a low voltage condition ...
Page 123
... Watchdog Options Watchdog Timer Function Enable 2. Disable CLRWDT Instructions Selection instructions 2. 2 instructions LVR Options LVR Function Enable 2. Disable LVR Voltage Selection: 1. 2.10V 8 2. 2.55V 3. 3.15V 4. 4.20V Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Options : OSC configuration option. OSC 123 www.DataSheet4U.com April 16, 2010 ...
Page 124
... Recommended component for added ESD protection. Note: ²**² Recommended component in environments where power line noise is significant. HT68F03/HT68F04 m ²*² Recommended component for added ESD protection. Note: ²**² Recommended component in environments where power line noise is significant. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 ...
Page 125
... W i thi Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
Page 126
... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
Page 127
... For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Description 127 www.DataSheet4U.com Cycles ...
Page 128
... Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. [m] ¬ ACC ²AND² [m] Operation Affected flag(s) Z Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 128 www.DataSheet4U.com April 16, 2010 ...
Page 129
... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 129 www.DataSheet4U.com April 16, 2010 ...
Page 130
... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ¬ 0 Operation PDF ¬ 1 Affected flag(s) TO, PDF Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 130 www.DataSheet4U.com April 16, 2010 ...
Page 131
... No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. ACC ¬ ACC ²OR² [m] Operation Affected flag(s) Z Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 131 www.DataSheet4U.com April 16, 2010 ...
Page 132
... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. ACC.(i+1) ¬ [m]. 0~6) Operation ACC.0 ¬ [m].7 Affected flag(s) None Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 132 www.DataSheet4U.com April 16, 2010 ...
Page 133
... Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ¬ [m].(i+1 0~6) Operation ACC.7 ¬ ¬ [m].0 Affected flag(s) C Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 133 www.DataSheet4U.com April 16, 2010 ...
Page 134
... Set Data Memory Description Each bit of the specified Data Memory is set to 1. [m] ¬ FFH Operation Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. [m].i ¬ 1 Operation Affected flag(s) None Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 134 www.DataSheet4U.com April 16, 2010 ...
Page 135
... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ¬ ACC - x Operation Affected flag(s) OV, Z, AC, C Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 135 www.DataSheet4U.com April 16, 2010 ...
Page 136
... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ¬ program code (low byte) Operation TBLH ¬ program code (high byte) Affected flag(s) None Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 136 www.DataSheet4U.com April 16, 2010 ...
Page 137
... Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² x Operation Affected flag(s) Z Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 137 www.DataSheet4U.com April 16, 2010 ...
Page 138
... Package Information 10-pin MSOP Outline Dimensions Symbol Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 Dimensions in mm Min. Nom. ¾ ¾ ¾ 0.00 ¾ 0.75 ¾ 0.17 ¾ ¾ ¾ 3.0 ¾ 4.9 ¾ 3.0 ¾ 0.5 ¾ 0.4 ¾ 0.95 ¾ 0° 138 www.DataSheet4U.com q Max. 1.10 0.15 0.95 0.27 0.25 ¾ ¾ ¾ ¾ ...
Page 139
... Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT66F03/HT66F04/HT68F03/HT68F04 139 www.DataSheet4U.com April 16, 2010 ...