HT68F04 Holtek Semiconductor, HT68F04 Datasheet - Page 99

• Manufacturer Part Number: HT68F04
• Description: Small Package Enhanced Flash Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

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A/D Operation
The START bit in the ADCR0 register is used to start
and reset the A/D converter. When the microcontroller
sets this bit from low to high and then low again, an ana-
log to digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR0 register will be set high and
the analog to digital converter will be reset. It is the
START bit that is used to control the overall start opera-
tion of the internal analog to digital converter.
The EOCB bit in the ADCR0 register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR0 register to check
whether it has been cleared as an alternative method of
detecting the end of an A/D conversion cycle.
Rev. 1.00
ACERL Register
¨
Bit 7~4
Bit 3
Bit 2
Bit 1
Bit 0
HT66F03/HT66F04
Name
POR
R/W
Bit
unimplemented, read as ²0²
ACE3: Define PA3 is A/D input or not
ACE2: Define PA2 is A/D input or not
ACE1: Define PA1 is A/D input or not
ACE0: Define PA0 is A/D input or not
0: Not A/D input
1: A/D input, AN3
0: Not A/D input
1: A/D input, AN2
0: Not A/D input
1: A/D input, AN1
0: Not A/D input
1: A/D input, AN0
¾
¾
¾
7
¾
¾
¾
6
¾
¾
¾
5
HT66F03/HT66F04/HT68F03/HT68F04
99
¾
¾
¾
4
The clock source for the A/D converter, which originates
from the system clock f
f
value is determined by the ADCK2~ADCK0 bits in the
ADCR1 register.
Although the A/D clock source is determined by the sys-
tem clock f
some limitations on the maximum A/D clock source
speed that can be selected. As the minimum value of per-
missible A/D clock period, t
taken for system clock frequencies equal to or greater
than 4MHz. For example, if the system clock operates at
a frequency of 4MHz, the ADCK2~ADCK0 bits should
not be set to ²000². Doing so will give A/D clock periods
that are less than the minimum A/D clock period which
may result in inaccurate A/D conversion values. Refer to
the following table for examples, where values marked
with an asterisk * show where, depending upon the de-
vice, special care must be taken, as the values may be
less than the specified minimum A/D Clock Period.
SYS
or a subdivided version of f
ACE3
R/W
3
1
SYS
, and by bits ADCK2~ADCK0, there are
ACE2
R/W
2
1
SYS
, can be chosen to be either
ADCK
, is 0.5ms, care must be
ACE1
SYS
R/W
1
1
. The division ratio
April 16, 2010
www.DataSheet4U.com
ACE0
R/W
0
1