UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 58

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table 45. Timer 1-Generated Commonly Used Baud Rates
The timer can be configured for either “timer” or
“counter” operation. In the most typical applica-
tions, it is configured for “timer” operation (C/T2 =
0). “Timer” operation is a little different for Timer 2
when it’s being used as a baud rate generator.
Normally, as a timer it would increment every ma-
chine cycle (thus at the 1/6 the CPU clock frequen-
cy). In the case, the baud rate is given by the
formula:
Mode 1,3 Baud Rate =
f
where (RCAP2H, RCAP2L) is the content of
RC2H and RC2L taken as a 16-bit unsigned inte-
ger.
Timer 2 also be used as the Baud Rate Generating
Mode. This mode is valid only if RCLK + TCLK = 1
in T2CON or in PCON.
Note: A roll-over in TH2 does not set TF2, and will
not generate an interrupt. Therefore, the Timer In-
terrupt does not have to be disabled when Timer 2
is in the Baud Rate Generator Mode.
Note: If EXEN2 is set, a 1-to-0 transition in T2EX
will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when
Timer 2 is in use as a baud rate generator, T2EX
can be used as an extra external interrupt, if de-
sired.
It should be noted that when Timer 2 is running
(TR2 = 1) in “timer” function in the Baud Rate Gen-
erator Mode, one should not try to READ or
WRITE TH2 or TL2. Under these conditions the
58/170
OSC
Mode 0 Max: 1MHz
Mode 2 Max: 375K
Modes 1, 3: 62.5K
/ (32 x [65536 – (RCAP2H, RCAP2L)]
Baud Rate
19.2K
137.5
9.6K
4.8K
2.4K
1.2K
110
110
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
12MHz
12MHz
12MHz
12MHz
6MHz
f
OSC
SMOD
X
1
1
1
0
0
0
0
0
0
0
timer is being incremented every state time, and
the results of a READ or WRITE may not be accu-
rate. The RC registers may be read, but should not
be written to, because a WRITE might overlap a
reload and cause WRITE and/or reload errors.
Turn the timer off (clear TR2) before accessing the
Timer 2 or RC registers, in this case.
More About Mode 0. Serial data enters and exits
through RxD. TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The
baud rate is fixed at 1/12 the f
Figure 27., page 61
diagram of the serial port in Mode 0, and associat-
ed timing.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal at S6P2 also loads a '1' into the
9th position of the transmit shift register and tells
the TX Control block to commence a transmission.
The internal timing is such that one full machine
cycle will elapse between “WRITE to SBUF” and
activation of SEND.
SEND enables the output of the shift register to the
alternate out-put function line of RxD and also en-
able SHIFT CLOCK to the alternate output func-
tion line of TxD. SHIFT CLOCK is low during S3,
S4, and S5 of every machine cycle, and high dur-
ing S6, S1, and S2. At S6P2 of every machine cy-
cle in which SEND is active, the contents of the
transmit shift are shifted to the right one position.
C/T
X
X
0
0
0
0
0
0
0
0
0
shows a simplified functional
Timer 1
Mode
X
X
2
2
2
2
2
2
2
2
1
OSC
.
Reload Value
FEEBh
FFh
FDh
FDh
E8h
1Dh
FAh
F4h
72h
X
X