AN1178 STMicroelectronics, AN1178 Datasheet - Page 21

• Manufacturer Part Number: AN1178
• Description: 80C32-PSD8XX DESIGN GUIDE
• Manufacturer: STMicroelectronics

Figure 9. Memory Map After Moving the Boot Flash Memory to Data Space
In this final configuration, the 80C32 has available:
32 Kbytes main Flash memory (fs0 and fs1) in the bottom of Program Space common to all pages
96 Kbytes main Flash memory in Program Space across three pages (8000h-FFFFh)
2 Kbytes of SRAM in addition to the SRAM that resides on the 80C32
16 Kbytes of secondary Flash memory for general data storage in Data Space (C000h-FFFFh)
16 Kbytes of secondary Flash memory for boot and ISP loader code in Data Space (8000h-FFFFh).
Each time this 80C32 system gets reset or goes through a power-on cycle, the PSD presents the memory
map of Figure 6 to the MCU, and the boot sequence is repeated.
PSDsoft Express Design Entry
The steps to implement the second design in PSDsoft Express are almost identical to those in the first
design. In fact, you can repeat the steps outlined in Sections 3.2.1 to 3.2.3, except you should give your
new project a different name. Then, when you are presented with the “MCU Template Selection” screen,
you should select “Advanced IAP, page & swap”.
Differences to note:
You will notice that in the “Page Register Definition” screen in the Design Assistant, there are two new
added bits: “swap” and “unlock”. These bits are used in the chip select equations to implement memory
swapping and control of which secondary memory section is made available in Data Space. Notice how
8000
FFFF
C000
4000
0000
Page 0
Map-
ped
Not
Program Space
(Flash Sector 1)
(Flash Sector 0)
Page 1
16 KByte
Page 1
16 KByte
FS2
FS3
16 KBytes
16 KBytes
FS1
FS0
Page 2
16 KByte
Page 2
16 KByte
FS5
FS4
Page 3
16 KByte
Page 3
16 KByte
FS7
FS6
VM Register = 0Ch
unlock = 0 or 1
Not to
swap = 1
Scale
C000
8000
2800
2000
0400
0300
0200
0000
FFFF
E000
A000
Optional Boot Flash/EEPROM
Optional Boot Flash/EEPROM
Optional Boot Flash/EEPROM
Optional Boot Flash/EEPROM
PSD Control Register (CSIOP)
AN1178 - APPLICATION NOTE
LCD Chip Select (CSLCD)
Optional SRAM (RS0)
CSBOOT3/EES3
CSBOOT2/EES2
CSBOOT1/EES1
CSBOOT0/EES0
Unmapped
Unmapped
8xC51 RAM
Data Space
22 KBytes
256 Bytes
256 Bytes
8 KBytes
8 KBytes
8 KBytes
8 KBytes
2 KBytes
AI03349B
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