FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 131

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

The Configuration of the FDC37B77x is very
flexible and is based on the configuration
architecture implemented in typical Plug-and-
Play components. The FDC37B77x is designed
for motherboard applications in which the
resources required by their components are
known.
architecture, the FDC37B77x allows the BIOS to
assign resources at POST.
SYSTEM ELEMENTS
Primary Configuration Address Decoder
After a hard reset (RESET_DRV pin asserted) or
Vcc Power On Reset the FDC37B77x is in the
Run Mode with all logical devices disabled. The
logical devices may be configured through two
standard Configuration I/O Ports (INDEX and
DATA)
Configuration Mode.
Entering the Configuration State
The device enters the Configuration State when
the following Config Key is successfully written
to the CONFIG PORT.
Note 1:
Note 2:
CONFIG PORT (Note
2)
INDEX PORT (Note 2)
DATA PORT
Config Key = < 0x55 >
by
With its flexible resource allocation
PORT NAME
placing
If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use
10K pull-down.
The configuration port base address can be relocated through CR26 and CR27.
the
The BIOS uses these
FDC37B77x
PULL-DOWN RESISTOR
SYSOPT= 0
(NOTE 1)
CONFIGURATION
0x03F0
0x03F0
into
INDEX PORT + 1
131
configuration ports to initialize the logical
devices at POST. The INDEX and DATA ports
are only valid when the FDC37B77x is in
Configuration Mode.
The SYSOPT pin is latched on the falling edge
of the RESET_DRV or on Vcc Power On Reset
to determine the configuration register's base
address. The SYSOPT pin is used to select the
CONFIG PORT's I/O address at power-up.
Once powered up the configuration port base
address can be changed through configuration
registers CR26 and CR27. The SYSOPT pin is
a hardware configuration pin which is shared
with the nRTS1 signal on pin 87. During reset
this pin is a weak active low signal which sinks
30µA. Note: All I/O addresses are qualified with
AEN.
The INDEX and DATA ports are effective only
when the chip is in the Configuration State.
Exiting the Configuration State
The device exits the Configuration State when
the following Config Key is successfully written
to the CONFIG PORT.
Config Key = < 0xAA>
10K PULL-UP
SYSOPT= 1
RESISTOR
0x0370
0x0370
Read/Write
Read/Write
TYPE
Write