FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 118

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

17.9.2 8042 P12 and P16 Functions
SMSC FDC37C672
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0
of the Port 92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is
output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration.
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode
compatible software.
controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register
forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the keyboard
controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high
drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon
reset, this signal is driven low.
8042 functions P12 and P16 are implemented as in a true 8042 part. Reference the 8042 spec for all
timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the
output to 1 within 20-30nsec. After several (# TBD) clocks, the port enable goes away and the internal
90µA pull-up maintains the output signal as 1.
In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the
port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the
output tristates: an external pull-up can pull the pin high, and the pin can be shared i.e., P12 and nSMI can
be externally tied together. In 8042 mode, the pins cannot be programmed as input nor inverted through
the GP configuration registers.
P92
Note: When Port 92 is disabled,
writes are ignored and reads
return undefined values.
8042
Bit 0
P20
This signal is externally OR’ed with the A20GATE signal from the keyboard
Pulse
Gen
KRESET Generation
14us
KRST_GA20
DATASHEET
Bit 2
Page 118
6us
14us
KRST
nALT_RST
6us
Enhanced Super I/O Controller with Fast IR
KBDRST
Rev. 10-29-03
Datasheet