FDC37M60X SMSC Corporation, FDC37M60X Datasheet - Page 21

• Manufacturer Part Number: FDC37M60X
• Description: ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
• Manufacturer: SMSC Corporation

DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset.
data
Configuration Control Register (CCR) not the
DSR,
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250 Kbps after a
hardware reset.
BIT 2 through 4
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal.
precompensation values for the combination of
these bits settings.
starting track number to start precompensation.
the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into manual low power mode. The
floppy controller
DSR is Shadowed in the Floppy Data Rate
Select
this starting track number can be changed by
rate
RESET
COND.
Shadow
for
See Table 11 for the settings
is
RESET
PC/AT
clock
S/W
programmed
Register,
7
0
Track 0 is the default
PRECOMPENSATION
Table 10 shows the
and data Note: The
POWER
and
DOWN
6
0
LD8:CRC2[7:0],
PS/2
using
5
0
0
Model
The
the
COMP2
PRE-
21
4
0
30 and Microchannel applications.
applications can set the data rate in the DSR.
The data rate of the floppy controller is the most
recent write of either the DSR or CCR. The DSR
is unaffected by a software reset. A hardware
reset
corresponds to the default precompensation
setting and 250 Kbps.
separator circuits will be turned off.
controller will come out of manual low power
mode after a software reset or access to the
Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is
self clearing.
Default: See Table 12
*2Mbps data rate is only available if Vcc= 5V.
PRECOMP
COMP1
Table 10 - Precompensation Delays
PRE-
432
111
001
010
011
100
101
110
000
will
3
0
set
COMP0
PRE-
PRECOMPENSATION DELAY
the
2
0
<2Mbps
Default
125.00
166.67
208.33
250.00
41.67
83.34
0.00
DSR
DRATE
SEL1
1
1
(nsec)
to
DRATE
SEL0
02H,
2Mbps*
Default
0
0
104.2
20.8
41.7
62.5
83.3
125
0
Other
which
The