IDT7205L12JG IDT, Integrated Device Technology Inc, IDT7205L12JG Datasheet - Page 10

• Manufacturer Part Number: IDT7205L12JG
• Description: IC FIFO 4096X18 12NS 32PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT7205L12JG

• Function: Asynchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 40MHz
• Access Time: 12ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 7205L12JG

NOTE:
1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.
Figure 13. Block Diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 FIFO Memory Used in Width Expansion Mode
USAGE MODES:
Width Expansion
control signals of multiple devices. Status flags (EF, FF and HF) can be detected
from any one device. Figure 13 demonstrates an 18-bit word width by using
two IDT7203/7204/7205/7206/7207/7208s. Any word width can be attained
by adding additional IDT7203/7204/7205/7206/7207/7208s (Figure 13).
Bidirectional Operation
system capable of Read and Write operations) can be achieved by pairing
IDT7203/7204/7205/7206/7207/7208s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Data Flow-Through
write flow-through mode. For the read flow-through mode (Figure 17), the
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Do not connect any output signals together.
Word width may be increased simply by connecting the corresponding input
Applications which require data buffering between two systems (each
Two types of flow-through modes are permitted, a read flow-through and
Figure 12. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 FIFO Used in Single Device Mode
FULL FLAG (FF)
DATA
RESET (RS)
WRITE (W)
IN
FULL FLAG (FF)
(D)
DATA IN (D)
RESET (RS)
WRITE (W)
18
(HALF-FULL FLAG)
EXPANSION IN (XI)
9
9
7203
7204
7205
7206
7207
7208
IDT
HF
XI
7203
7204
7205
7206
7207
7208
(HF)
9
IDT
10
9
FIFO permits a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (t
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after t
deassertion and then would be asserted.
a single word of data immediately after reading one word of data from a full FIFO.
The R line causes the FF to be deasserted but the W line being LOW causes
it to be asserted again in anticipation of a new data word. On the rising edge of
W, the new word is loaded in the FIFO. The W line must be toggled when FF
is not asserted to write new data in the FIFO and to increment the write pointer.
Compound Expansion
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
In the write flow-through mode (Figure 18), the FIFO permits the writing of
The two expansion techniques described above can be applied together
9
7203
7204
7205
7206
7207
7208
HF
IDT
RHZ
XI
ns. The EF line would have a pulse showing temporary
READ (R)
RETRANSMIT (RT)
DATA OUT (Q)
EMPTY FLAG (EF)
COMMERCIAL, INDUSTRIAL AND MILITARY
9
18
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DATA
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
TEMPERATURE RANGES
WEF
OUT
+ t
(Q)
A
) ns after the rising
JUNE 11, 2009
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